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www.latticesemi.com 1 gdx2fam_09 ispgdx2 f amily high performance interfacing and switching ju ly 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. includ es high- performan ce, low-co st ?e? series features ? high performance bus switching ? high bandwidth ? up to 12.8 gbps (serdes) ? up to 38 gbps (without serdes) ? up to 16 (15x10) fifos for data buffering ? high speed performance ?f max = 360mhz ?t pd = 3.0ns ?t co = 2.9ns ?t s = 2.0ns ? built-in programmable control logic capability ? i/o intensive: 64 to 256 i/os ? expanded mux capability up to 188:1 mux sysclock? pll ?f requency synthesis and skew management ? clock multiply and divide capability ? clock shifting up to +/-2.35ns in 335ps steps ? up to four plls sysio? interfacing ?l vcmos 1.8, 2.5, 3.3 and lvttl support for standard board interfaces ? sstl 2/3 class i and ii support ? hstl class i, iii and iv support ? gtl+, pci-x for bus interfaces ?l vpecl, lvds and bus lvds differential support ? hot socketing ? programmable drive strength tw o options available ? high-performance syshsi (standard part number) ?l o w-cost, no syshsi (?e? series) syshsi blocks provide up to 16 high-speed channels ? serializer/de-serializer (serdes) included ? clock data recovery (cdr) built in ? 800 mbps per channel ?l vds differential support ? 10b/12b support - encoding / decoding - bit alignment - symbol alignment ? 8b/10b support - bit alignment - symbol alignment ? source synchronous support flexible programming and testing ? ieee 1532 compliant in-system programmabil- ity (isp?) ? boundary scan test through ieee 1149.1 interface ? 3.3v, 2.5v or 1.8v power supplies ? 5v tolerant i/o for lvcmos 3.3 and lvttl interfaces ta b le 1. ispgdx2 family selection guide ispgdx2-64/e ispgdx2-128/e ispgdx2-256/e i/os 64 128 256 gdx blocks 4 8 16 t pd 3.0ns 3.2ns 3.5ns t s 2.0ns 2.0ns 2.0ns t co 2.9ns 3.1ns 3.2ns f max (toggle) 360mhz 330mhz 300mhz max bandwidth serdes 1, 2 3.2gbps 6.4gbps 12.8gbps without serdes 3 11gbps 21gbps 38gbps syshsi channels 2 4816 l vds/bus lvds (pairs) 32 64 128 plls 2 2 4 pa c kage 100-ball fpbga 208-ball fpbga 484-ball fpbga 1. max number of serdes channels per device * 800mbps 2. ?e? series does not support syshsi. 3. f max (toggle) * maximum i/os divided by 2.
lattice semiconductor ispgdx2 family data sheet 2 figure 1. ispgdx2 block diagram (256-i/o device) introduction the ispgdx2? family is lattice?s second generation in-system programmable generic digital crosspoint switch for high speed bus switching and interface applications. the ispgdx2 family is available in two options. the standard device supports syshsi capability for ultra fast serial communications while the lower-cost ?e? series supports the same high-performance fpga fabric without the syshsi block. this family of switches combines a e xible switching architecture with advanced sysio interfaces including high performance syshsi blocks, and sysclock plls to meet the needs of the today?s high-speed systems. through a muliplexer-intensive architecture, the ispgdx2 facilitates a variety of common switching functions. the availability of on-chip control logic further enhances the power of these devices. a high-performance solution, the family supports bandwidth up to 38gbps. every device in the family has a number of plls to provide the system designer with the ability to generate multiple clocks and manage clock skews in their systems. gdx block sysclock pll sysclock pll serdes sysio bank sysio bank sysio bank sysio bank serdes gdx block serdes gdx block serdes serdes serdes serdes serdes gdx block gdx block gdx block gdx block gdx block fifo fifo fifo fifo fifo fifo fifo fifo isp & boundary scan t est port gdx block serdes sysio bank sysio bank serdes gdx block serdes gdx block serdes gdx block fifo fifo fifo fifo sysio bank sysio bank serdes serdes serdes serdes gdx block gdx block gdx block gdx block fifo fifo fifo fifo syshsi block syshsi block syshsi block syshsi block syshsi block syshsi block syshsi block syshsi block sysclock pll sysclock pll global routing pool (grp)
lattice semiconductor ispgdx2 family data sheet 3 the sysio interfaces provide system-level performance and integration. these i/os support various modes of l vcmos/lvttl and support popular high-speed standard interfaces such as gtl+, pci-x, hstl, sstl, lvds and bus-lvds. the syshsi blocks further extend this capability by providing high speed serial data transfer capa- bility. devices in the family can operate at 3.3v, 2.5v or 1.8v core voltages and can be programmed in-system via an ieee 1149.1 interface that is compliant with the ieee 1532 standard. voltages required for the i/o buffers are inde- pendent of the core voltage supply. this further enhances the e xibility of this family in system designs. t ypical applications for the ispgdx2 include multi-port multi-processor interfaces, wide data and address bus mul- tiplexing, programmable control signal routing and programmable bus interfaces. table 1 shows the members of the ispgdx2 family and their key features. architecture the ispgdx2 devices consist of gdx blocks interconnected by a global routing pool (grp). signals interface with the external system via sysio banks. in addition, each gdx block is associated with a fifo and a syshsi block to facilitate the transfer of data on- and off-chip. figure 1 shows the ispgdx2 block diagram. each gdx block can be individually con gured in one of four modes: ? basic (no fifo or serdes) ? fifo only ? serdes only ? serdes and fifo each sysio bank has its own i/o power supply and reference voltage. designers can use any output standard within a bank that is compatible with the power supply. any input standard may be used, providing it is compatible with the reference voltage. the banks are independent. global routing pool (grp) the ispgdx2 architecture is organized into gdx blocks, which are connected via a global routing pool. the inno- v ative grp is optimized for routability, e xibility and speed. all the signals enter via the gdx block. the block sup- plies these either directly or in registered form to the grp. the grp routes the signals to different blocks, and provides separate data and control routing. the data path is optimized to achieve faster speed and routing e xibility f or nibble oriented signals. the control routing is optimized to provide high-speed bit oriented routing of control sig- nals. there are some restrictions on the allocation of pins for optimal bus routing. these restrictions are considered by the software in the allocation of pins. gdx block the blocks are organized in a ?block? (nibble) manner, with each gdx block providing data ow and control logic f or 16 i/o buffers. the data ow is organized as four nibbles, each nibble containing four multiplexer register blocks (mrbs). data for the mrbs is provided from 64 lines from the grp. figure 2 illustrates the groups of signals going into and out of a gdx block. control signals for the mrbs are provided from the control array. the control array receives the 32 signals from the grp and generates 16 control signals: eight mux select, four clock/clock enable, two set/reset and two out- put enable. each nibble is controlled via two mux select signals. the remaining control signals go to all the mrbs. besides the control signals from the control array, the following global signals are available to the mrbs in each gdx block: four clock/clock enable, one reset/preset, one power-on reset, two of four mux select (two of two in 64 i/o), four output enable (two in 64 i/o) and test out enable (toe).
lattice semiconductor ispgdx2 family data sheet 4 mux and register block (mrb) every mrb block has a 4:1 mux (i/o mux) and a set of three registers which are connected to the i/o buffers, fifo and syshsi blocks. multiple mrbs can be combined to form large multiplexers as described below. figure 3 shows the structure of the mrb. each of the three registers in the mrb can be con gured as edge-triggered d-type ip- op or as a level sensitive latch. one register operates on the input data, the other output data and the last register synchronizes the output enable function. the input and output data signals can bypass each of their registers. the polarity of the data out and output enable signals can be selected. the output and oe register share the same clock and clock enable signals. the input register has a separate clock and clock enable. the initialization signals of each register can be independently con gured as set or reset. these registers have programmable polarity control for clock, clock enable and set/reset. the output enable register input can be set either by one of the two output enables generated locally from the control array or from one of the f our (two in 64 i/o) global oe enable pins. in addition to the local clock and clock enable signals, each mrb has access to global clock, clock enable, reset and toe nets.
lattice semiconductor ispgdx2 family data sheet 5 figure 2. gdx block the output register of the mrb has a built-in bi-directional shift register capability. each output register correspond- ing to mrb ?n?, receives data output from its two adjacent mrbs, mrb (n-1) and mrb (n+1), to provide shift regis- ter capability. like the output register, each input register of the mrb has built-in shift register capability. each input register can receive data from its two adjacent mrb input registers, to provide bi-directional shift register capability. the chaining crosses gdx block boundaries. the chain of input registers and the chain of output registers can be combined as one shift register via the grp. mux and register block (mrb) 0 oe in out oe in out oe in out oe in out oe in out oe in out oe in out mux and register block (mrb) 1 mux and register block (mrb) 2 gdx block grp sysio bank 32 bits control mux select 16 bits 16 bits 16 bits 4 bits 4 bits 4 bits 4 bits 8 2 mux and register block (mrb) 3 control array 8 2 2 8 2 8 2 8 2 8 8 8 8 2 4 4 4 nibble 3 mrbs 12-15 nibble 2 mrbs 8-11 nibble 1 mrbs 4-7 nibble 0
lattice semiconductor ispgdx2 family data sheet 6 the four data inputs to the 4:1 mux come from the grp. the output of this mux connects to the output register. a f ast feedback path from the mux to the grp allows wider muxes to be built. table 2 summarizes the various mux sizes and delay levels. ta b le 2. mux size versus internal delay figure 3. ispgdx2 family mrb control array the control array generates control signals for the 16 mrbs within a gdx block. the true and complement forms of 32 inputs from the grp are available in the control array. the 20 nand terms can use any or all of these inputs to form the control array outputs. two and terms are combined with a nor term to form set/reset and oe sig- nals. figure 4 illustrates the control array. mux sizes levels of internal grp delays 4:1 one level up to 16:1 two levels up to 64:1 three levels up to 188:1 (with ispgdx2-256) four levels oe reg/latch oe ce ck ck ce s/r s/r d/l clk ce set reset d/l clk ce set reset q q 2 4 2 2-4 4 set/reset ck/ce ck/ce oe oe to in_reg(n-1) to in_reg(n+1) from out_reg(n-1) from out_reg(n+1) fifo out* from in_reg(n-1) from in_reg(n+1) to out_reg(n-1) to out_reg(n+1) flags* (fifo, serdes or pll) *selected mrbs see logic signal connection table for details v cc v cc delay global resetb global resetb f rom grp mux select control array signals mux select global signals global signals gdx control array toe to grp d/l clk ce set reset q out reg/latch input reg/latch
lattice semiconductor ispgdx2 family data sheet 7 figure 4. ispgdx2 family control array sysio banks the inputs and outputs of ispgdx2 devices are divided into eight sysio banks, where each bank is capable of sup- porting different i/o standards. the number of i/os per bank is 32, 16 and 8 for the 256-, 128- and 64-i/o devices respectively. each sysio bank has its own i/o supply voltage (v cco ) and reference voltage (v ref ), allowing each bank complete independence from the other banks. each i/o within a bank can be individually con gured to any standard consistent with the v cco and v ref settings. figure 5 shows the i/o banks for the ispgdx2-256 device. the i/o of the ispgdx2 devices contain a programmable strength and slew rate tri-state output buffer, a program- mable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus- k eeper latch. these programmable capabilities allow the support of a wide range of i/o standards. mux select to nibble 0 mux select to nibble 1 mux select to nibble 2 mux select to nibble 3 to mrb clock/ clock enable to mrb set/reset to mrb output enable 32 inputs from control grp each connection is programmable. on selected blocks, this signal can reset the m divider of the pll.
lattice semiconductor ispgdx2 family data sheet 8 figure 5. ispgdx2-256 sysio banks there are three classes of i/o interface standards implemented in the ispgdx2 devices. the rst is the non-termi- nated, single-ended interface; it includes the 3.3v lvttl standard along with the 1.8v, 2.5v and 3.3v lvcmos interface standards. the slew rate and strength of these output buffers can be controlled individually. additionally, pci 3.3, pci-x and agp-1x are all subsets of this interface type. the second interface class implemented is the terminated, single-ended interface standard. this group of interfaces includes different versions of sstl and hstl interfaces along with ctt and gtl+. use of these i/o interfaces requires an additional v ref signal. at the system level, a termination voltage, v tt , is also required. typically, an output will be terminated to v tt at the receiving end of the transmission line it is driving. the nal types of interfaces implemented are the differential standards l vpecl, lvds and bus lvds. table 3 shows the i/o standards supported by the ispgdx2 devices along with nominal v cco , v ref and v tt . the ispgdx2 family also features 5v tolerant i/o. i/o banks with v cco = 3.3v may have inputs driven to a maxi- m um of 5.5v for easy interfacing with legacy systems. up to 64 i/o pins per device may be driven by 5v inputs. sysio bank 5 sysio bank 6 sysio bank 2 sysio bank 1 sysio bank 7 sysio bank 0 sysio bank 4 sysio bank 3 v cco5 v ref5 gnd v cco3 v ref3 gnd v cco0 v ref0 gnd v cco7 v ref7 gnd v cco4 v ref4 gnd v cco2 v ref2 gnd v cco6 v ref6 gnd v cco1 v ref1 gnd
lattice semiconductor ispgdx2 family data sheet 9 ta b le 3. ispgdx2 supported i/o standards the dedicated inputs support a subset of the sysio standards indicated in table 4. these inputs are associated with a bank consistent with their location. ta b le 4. i/o standards supported by dedicated inputs f or more information on the sysio capability, please refer to lattice technical note number tn1000, sysio design and usage guidelines. sysclock pll the sysclock pll circuitry consists of phase-lock loops (plls) along the various dividers and reset and feed- back signals associated with the plls. this feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. furthermore, it can generate clock signals that are deskewed either at the board level or the device level. figure 6 shows the ispgdx2 pll block diagram. each pll has a set of pll_rst, pll_fbk and pll_lock signals. in order to facilitate the multiply and divide capabilities of the pll, each pll has associated dividers. the m divider is used to divide the clock signal, while the sysio standard nominal v cco nominal v ref nominal v tt l vcmos 3.3 3.3v ? ? l vcmos 2.5 2.5v ? ? l vcmos 1.8 1.8v ? ? l vttl 3.3v ? ? pci 3.3 3.3v ? ? pci -x 3.3v ? ? a gp-1x 3.3v ? ? sstl3 class i & ii 3.3v 1.5v 1.5v sstl2 class i & ii 2.5v 1.25v 1.25v ctt 3.3 3.3v 1.5v 1.5v ctt 2.5 2.5v 1.25v 1.25v hstl class i 1.5v 0.75v 0.75v hstl class iii 1.5v 0.9v 0.75v hstl class iv 1.5v 0.9v 1.5v gtl+ 1.8/2.5/3.3v 1.0v 1.5v l vpecl 1, 2, 3 3.3v ? ? l vds 2.5/3.3v ? ? bus-lvds 2.5/3.3v ? ? 1. lvpecl drivers require three resistor pack (see figure 16). 2. depending on the driving lvpecl output speci cation, gdx2 lvpecl input driver may require terminating resistors. 3. for additional information on lvpecl refer to lattice technical note number tn1000, sysio design and usage guidelines. l vcmos lvds all other asic i/os global oe pins yes no yes 2 global mux select pins yes no yes 2 resetb yes no yes 2 global clock/clock enables yes yes yes 2 ispjtag? port yes 1 no no toe yes no no 1. lvcmos as de ned by the v ccj pin voltage. 2. no pci clamp.
lattice semiconductor ispgdx2 family data sheet 10 n divider is used to multiply the clock signal. the k divider is used to provide a divided clock frequency of the adja- cent pll. this output can be routed to the global clock net. the v divider is used to provide lower frequency output clocks, while maintaining a stable, high frequency output from the pll?s vco circuit. the pll also has a delay fea- ture that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better per- fo r mance. for more information on the pll, please refer to lattice technical note number tn1003, sysclock pll design and usage guidelines . figure 6. sysclock pll there are four global clock networks routed to each mrb block. these global clocks, clk0-3, can either be gener- ated by the pll circuits or supplied externally. external clock pins can be con gured as single-ended or differential (lvds) input. figure 7 illustrates how the sysclock pll inputs and outputs can be routed to the i/o pins or gen- eral routing. figure 8 shows the clock network for the ispgdx2-256 and figure 9 shows the clock networks for ispgdx2-128 and ispgdx2-64. the reset (0) pin from the control array of selected gdx blocks can be pro- gr ammed to reset the m divider of the plls. this provides a means for generating the reset signal internally. ta b le 5 details which gdx block provides reset to the plls. ta b le 5. internal reset input of the pll (m divider) pll0 pll1 pll2 pll3 ispgdx2-256 gdx block 5a gdx block 7b gdx block 1a gdx block 3b ispgdx2-128 gdx block 2a ? gdx block 0a ? ispgdx2-64 gdx block 0a ? gdx block 1b ? gclk_in pll_rst pll_fbk pll_lock clk_out clock net input clock (m) divider 1 to 32 pll (n) programmable +delay -------------------- programmable -delay to a d j a cent_pll fe edback divider (n) x 1 to 32 p ost-scalar (v) divider 1, 2, 4, 8, 16, 32 clock (k) divider 2, 4, 8, 16, 32 f rom adjacent_pll
lattice semiconductor ispgdx2 family data sheet 11 figure 7. i/o pin connection to the sysclock pll 1 gdx block grp gclk_in pll_rst pll_fbk pll_lock clk_out fr om adjacent_pll input clock (m) divider 1 to 32 -------------------- to adjacent_pll clock net gclk_in input reg/ latch input reg/ latch delay delay control array (from selected blocks) 1. some pins are shared. see logic signal connections table for details. resetb (0) programmable + delay programmable - delay pll (n) po st-scalar (v) divider 1, 2, 4, 8, 16, 32 f eedback divider (n) x 1 to 32 clock (k) divider 2, 4, 8, 16, 32
lattice semiconductor ispgdx2 family data sheet 12 figure 8. ispgdx2-256 clock network clk_out0 + - pll (0) clock net reg/ latch clk0 gclk/ce0 vref0 k(0) clk_out1 + - pll (1) clock net reg/ latch clk1 gclk/ce1 vref1 k(1) clk_out2 + - pll (2) clock net reg/ latch clk2 gclk/ce2 vref2 k(2) clk_out3 + - pll (3) clock net reg/ latch clk3 gclk/ce3 vref3 k(3) sysio interface sysclock clock net mrb
lattice semiconductor ispgdx2 family data sheet 13 figure 9. ispgdx2-128 and 64 clock network clk_out0 + - pll (0) clock net reg/ latch clk0 gclk/ce0 vref0 k(0) + - clock net reg/ latch gclk/ce1 vref1 clk_out2 + - pll (2) clock net reg/ latch clk2 gclk/ce2 vref2 k(2) + - clock net reg/ latch gclk/ce3 vref3 sysio interface sysclock clock net mrb
lattice semiconductor ispgdx2 family data sheet 14 operating modes all the gdx blocks in the ispgdx2 family can be programmed in four modes: basic, fifo only, serdes only, and fifo with serdes mode. in basic mode, the serdes and fifo are disabled and the mux output of the mrb connects to the output register. inputs are connected to the grp via the mrb. figure 10 shows the four different operating modes. precise detail of the fifo and serdes connections is pro- vided in their respective sections. figure 10. four operating modes of ispgdx2 devices fifo operations each gdx block is associated with a 10-bit wide and 15-word deep (10x15) ram. this ram, combined with two address counters and two comparators, is used to implement a fifo as a ?circular queue?. the fifo has separate clocks, the read clock (rclk) and write clock (wclk), for asynchronous operation. the fifo has three addi- tional control signals write enable, read enable and fifo reset. three ags show the status of the fifo: empty, full and start read. each fifo receives the global power-on reset and reset signals. figure 11 shows the con- nections to the fifo. gdx block sysio bank basic mode grp serdes fifo gdx block sysio bank fifo mode grp serdes fifo gdx block sysio bank serdes mode (fifo in flow-through mode) grp serdes fifo* *fifo held in reset for serdes-onl y mode. gdx block sysio bank serdes and fifo mode grp serdes fifo
lattice semiconductor ispgdx2 family data sheet 15 figure 11. ispgdx2 fifo signals read clock and read enable are the same as the clock and clock enable signals of the input registers of the associated mrb. these registers are used to register the fifo outputs, and in modes that utilize the fifo are con- gured to use the same clock and clock enable signals. the write clock is selected from one of the gclk/ce sig- nals or the recclk (recovered clock) signal from the associated serdes. the write enable is selected from one of the local mrb product term clk/ce signals. all fifo operations occur on the rising edge of the clock although clock polarity of these signals can be programmed. the ags from the fifo, full, empty and strdb (start read) are each fed via a mux in the mrb to an i/o b uffer. the strdb (half full) signal is used in conjunction with serdes. strdb is an active low signal, the signal is inactive (high) on fifo reset. after the fifo reset when the fifo contains data in ve memory locations, at the following write clock transition the strdb becomes active (low). note, if the read clocks arrive before writing the sixth location, it may take longer than ve write clocks before the strdb becomes active. when the fifo has data in the rst six locations, at the next write clock transition the strdb becomes inactive (high). again, if the read clocks arrive before writing the seventh location, the strdb may stay active for longer than one write clock period, even if the fifo contains data in less than ve locations. after this event, the strdb stays inactive until the fifo is reset again. strdb does not become active again even if less than six memory locations are occupied in the fifo. it is the user?s responsibility to monitor the full and empty signals to avoid data under o w/over ow and to take appropriate actions. figure 12 shows how the fifo is connected between the i/o banks and the gdx blocks in fifo mode. for more information on the fifo, please refer to lattice technical note number tn1020, syshsi usage guidelines . fifo 10x15 data in (din) data out (dout) write clock (wclk) 10 10 write enable (we) full (full) empty (empty) read clock (rclk) read enable (re) global reset (resetb) power-on reset (porb) fifo reset (fiforstb) start read (strdb)
lattice semiconductor ispgdx2 family data sheet 16 figure 12. operation in fifo mode 2 serdes fifo gdx block 1 grp 10 serial data in (sin) serial data out (sout) rxd para llel data txd para llel data din dout rclk re fiforstb notes: 1. for clarity, only a portion of the gdx block is shown. 2. some signals share pins. see logic signal connections tables for details. sydt cdrrstb full empty output reg/ latch output reg/ latch output reg/ latch 10 input reg/ latch delay por resetb pre-assigned pins we pt-clk/ce(0:3) recclk wclk gclk/ce(0:3) input reg/ latch input reg/ latch cal 10
lattice semiconductor ispgdx2 family data sheet 17 high speed serial interface block (syshsi block) 1 the high speed serial interface (syshsi) allows high speed serial data transfer over a pair of lvds i/o. the ispgdx2 devices have multiple syshsi blocks. each syshsi block has two serdes blocks which contain two main sub-blocks, transmitter (with a serializer) and receiver (with a deserializer) including clock/data recovery circuit (cdr). each serdes can be used as a full duplex channel. the two serdes in a given syshsi block share a common clock and must operate at the same nominal frequency. figure 13 shows the syshsi block. device features support two data coding modes: 10b/12b and 8b/10b (for use with other encoding schemes, see lattice?s syshsi application notes). the encoding and decoding of the 10b/12b standard are performed within the device in dedicated logic. for the 8b/10b standard, the symbol boundaries are aligned internally but the encoding and decoding are performed outside the device. each serdes block receives a single high speed serial data input stream (with embedded clock) from an input, and provide a low speed 10-bit wide data stream and a recovered clock to the device. for transmitting, the ser- des converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output. additionally, multiple syshsi blocks can be grouped together to form a source synchronous interface of between 1- 8 channels. figure 14 shows the connections of the serdes block with the fifo, sysio block and the mrb. table 6 provides the descriptions of the serdes. f or more information on the serdes/cdr, refer to lattice technical note number tn1020, syshsi usage guide- lines . ta b le 6. serdes signal descriptions 1. ?e? series does not support syshsi. signal i/o description cdrrstb i resets the cdr circuit of syshsi block sydt o symbol alignment detect for syshsi block cal i initiates source synchronous calibration sequence rxd internal parallel data in for syshsi block txd internal parallel data out for syshsi block refclk internal reference clock received from the clock tree sin i serial data input for syshsi block (lvds input) sout o serial data output for syshsi block (lvds output) ss_clkin i clock input for source synchronous group ss_clkout o clock output for source synchronous group recclk internal recovered clock from encoded data by cdr of syshsi block cslock internal lock output of the pll associated with syshsi block
lattice semiconductor ispgdx2 family data sheet 18 figure 13. syshsi block with serdes and fifo syshsi block core logic cspll ss_clkout ss_clkin cal shared source synchronous pins drive multiple syshsi blocks cslock cslock txd rxd recclk serializer serdes sout sin fifo de-serializer including cdr 10 10 10 10 fifo refclk (0:3) reference clocks from clk (0:3) note: some pins are shared. see logic signal connections table for details gdx block gdx block grp serializer de-serializer including cdr txd rxd recclk sout sin serdes
lattice semiconductor ispgdx2 family data sheet 19 figure 14. operation in serdes only mode 1, 2 serdes fifo gdx block grp 10 serial data in (sin) serial data out (sout) rxd para llel data txd para llel data din dout rclk re fiforstb sydt cdrrstb full empty output reg/ latch output reg/ latch output reg/ latch 10 input reg/ latch delay por resetb pre-assigned pins we pt-clk/ce(0:3) recclk wclk gclk/ce(0:3) input reg/ latch input reg/ latch cal notes: 1. some pins shared. see logic signal connections table for details. 2. for serdes only mode programmable bit holds fifo in reset. input registers used for dout, and recclk configured as latches and held in pass through.
lattice semiconductor ispgdx2 family data sheet 20 figure 15. operation in serdes with fifo mode serdes fifo gdx block grp 10 serial data in (sin) serial data out (sout) rxd para llel data txd para llel data din dout rclk re fiforstb sydt cdrrstb full empty output reg/ latch output reg/ latch output reg/ latch 10 input reg/ latch delay por resetb pre-assigned pins we pt-clk/ce(0:3) recclk wclk gclk/ce(0:3) input reg/ latch input reg/ latch cal
lattice semiconductor ispgdx2 family data sheet 21 ieee 1149.1-compliant boundary scan testability all ispgdx2 devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows func- tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit- ical logic notes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri cation. in addition, these devices can be linked into a board-level serial scan path for more board-level testing. the test access port has its own supply voltage that can operate with lvcmos3.3, 2.5 and 1.8 standards. sysio quick con guration to f acilitate the most ef cient board test, the physical nature of the i/o cells must be set before running any continu- ity tests. as these tests are fast, by nature, the overhead and time that is required for con guration of the i/os' physical nature should be minimal so that board test time is minimized. the ispgdx2 family of devices allows this by offering the user the ability to quickly con gure the physical nature of the sysio cells. this quick con guration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. lattice's ispvm? system programming software can either perform the quick con guration through the pc parallel port, or can generate the ate or test vectors necessary for a third-party test system. ieee 1532-compliant in-system programming in-system programming of devices provides a number of signi cant bene ts including rapid prototyping, lower inventory levels, higher quality and the ability to make in- eld modi cations. all ispgdx2 devices provide in-system programming (isp) capability through their boundary scan test access port. this capability has been imple- mented in a manner that ensures that the port remains compliant to the ieee 1532 standard. by using ieee 1532 as the communication interface through which isp is achieved, designers get the bene t of a standard, well de ned interface. the ispgdx2 devices can be programmed across the commercial temperature and voltage range. the pc-based lattice software facilitates in-system programming of ispgdx2 devices. the software takes the jedec le output produced by the design implementation software, along with information about the scan chain, and creates a set of v ectors used to drive the scan chain. the software can use these vectors to drive a scan chain via the parallel port of a pc. alternatively, the software can output les in formats understood by common automated test equipment. this equipment can then be used to program ispgdx2 devices during the testing of a circuit board. security scheme a programmable security scheme is provided on the ispgdx2 devices as a deterrent to unauthorized copying of the array con guration patterns. once programmed, this scheme prevents readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. the security scheme also prevents program- ming and veri cation. the entire device must be erased in order to reset the security scheme. hot socketing the ispgdx2 devices are well suited for those applications that require hot socketing capability. hot socketing a device requires that the device, when powered down, can tolerate active signals on the i/os and inputs without being damaged. additionally, it requires that the effects of the powered-down device be minimal on active signals.
lattice semiconductor ispgdx2 family data sheet 22 absolute maximum ratings 1, 2, 3 ispgdx2c (1.8v) ispgdx2b/v (2.5/3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v . . . . . . . . . . . . . . . . -0.5 to 5.5v pll supply voltage v ccp . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v . . . . . . . . . . . . . . . . -0.5 to 5.5v output supply voltage v cco . . . . . . . . . . . . . . . . . -0.5 to 4.5v . . . . . . . . . . . . . . . . -0.5 to 4.5v jtag supply voltage (v ccj ) . . . . . . . . . . . . . . . . . -0.5 to 4.5v . . . . . . . . . . . . . . . . -0.5 to 4.5v input or i/o tristate voltage applied 4, 5 . . . . . . . . . -0.5 to 5.5v . . . . . . . . . . . . . . . . -0.5 to 5.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c . . . . . . . . . . . . . . . -65 to 150 c j unction temp. (t j ) with power applied . . . . . . . . -55 to 150 c . . . . . . . . . . . . . . . -55 to 150 c 1. stress above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation o f the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied (while program- ming, following the programming speci cations). 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. 4. overshoot and undershoot of -2v to (v ih (max)+2) volts is permitted for a duration of <20ns. 5. a maximum of 64 i/os per device with v in > 3.6v is allowed. recommended operating conditions erase reprogram speci cations hot socketing speci cations 1, 2, 3 symbol parameter min. max. units v cc supply voltage for 1.8v devices 1 1.65 1.95 v supply voltage for 2.5v devices 2.3 2.7 v supply voltage for 3.3v devices 3 3.6 v v ccp supply voltage for pll and syshsi blocks, 1.8v devices 1 1.65 1.95 v supply voltage for pll and syshsi blocks, 2.5v devices 2.3 2.7 v supply voltage for pll and syshsi blocks, 3.3v devices 3 3.6 v v ccj po w er supply voltage for jtag programming 1.8v operation 1.65 1.95 v po w er supply voltage for jtag programming 2.5v operation 2.3 2.7 v po w er supply voltage for jtag programming 3.3v operation 3 3.6 v t j (com) junction commercial operation 0 90 c t j (ind) junction industrial operation -40 105 c 1. syshsi speci cation is valid for v cc and v ccp = 1.7v to 1.9v. p arameter min max units erase/reprogram cycle 1,000 ? cycles note: valid over commercial temperature range. symbol parameter condition min typ max units i dk 4 input or tristated i/o leakage current 0 v in 3.0v ? +/-50 +/-800 a 1. insensitive to sequence of v cc and v cco . however, assumes monotonic rise/fall rates for v cc and v cco, provided (v in - v cco ) 3.6v. 2. lvttl, lvcmos only. 3. 0 < v cc v cc (max), 0 < v cco v cco (max). 4. i dk is additive to i pu , i pd or i bh . device defaults to pull-up until fuse circuitry is active.
lattice semiconductor ispgdx2 family data sheet 23 dc electrical characteristics over recommended operating conditions supply current over recommended operating conditions (ispgdx2-256) 4 symbol parameter condition min. typ. max. units i il , i ih 1 input or i/o low leakage 0 v in (v cco - 0.2v) ? ? 10 a (v cco - 0.2v) < v in 3.6v ? ? 30 a i ih 3 input high leakage current 3.6v < v in 5.5v and 3.0v v cco 3.6v ?? 3ma i pu i/o active pull-up current 0 v in 0.7 v cco -30 ? -150 a i pd i/o active pull-down current v il (max) v in v ih (max) 30 ? 150 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7 v cco -30 ? ? a i bhlo bus hold low overdrive current 0 v in v ih (max) ? ? 150 a i bhlh bus hold high overdrive current 0 v in v ih (max) ? ? -150 a v bht bus hold trip points v cco * 0.35 ? v cco * 0.65 v c 1 i/o capacitance 2 v cco = 3.3v, 2.5v, 1.8v ? 8 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? c 2 clock capacitance 2 v cco = 3.3v, 2.5v, 1.8v ? 6 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? c 3 global input capacitance 2 v cco = 3.3v, 2.5v, 1.8v ? 6 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? 1. input or i/o leakage current is measured with the pin con gured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a = 25 c, f = 1.0mhz. 3. 5v tolerant inputs and i/os should be placed in banks where 3.0v v cco 3.6v. the jtag ports are not included for the 5v tolerant inter- f ace. symbol description power pins vcc (v) min. typ. max. units i cc 1,2 core logic power supply current v cc 3.3 ? 59.6 ? ma 2.5 ? 58.7 ? ma 1.8 ? 60.0 ? ma gpll/syshsi logic power supply current 3.3 ? 118.7 ? ma 2.5 ? 118.7 ? ma 1.8 ? 117.5 ? ma i ccp 2 gpll/syshsi cspll power supply current v ccp 3.3 ? 14.7 ? ma 2.5 ? 14.7 ? ma 1.8 ? 17.4 ? ma i cco 3 bank power supply current v cco 3.3 ? 35 ? ma 2.5 ? 35 ? ma 1.8 ? 25 ? ma i ccj jtag programming current v ccj 3.3 ? 1.5 ? ma 2.5 ? 1.0 ? ma 1.8 ? 800 ? a 1. 64-input switching frequency at 20 mhz, with one grp fanout. 2. one gpll with f vco = 400 mhz and one syshsi block (two receivers and two transmitters) at 622 mhz data rate. 3. all 8-bank reference circuit currents, all i/os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled. 4. t a = 25c
lattice semiconductor ispgdx2 family data sheet 24 sysio recommended operating conditions standard v cco (v) 1 v ref (v) min. typ. max. min. typ. max. l vcmos 3.3 3.0 3.3 3.6 - - - l vcmos 2.5 2.3 2.5 2.7 - - - l vcmos 1.8 2 1.65 1.8 1.95 - - - l vttl 3.0 3.3 3.6 - - - pci 3.3 3.0 3.3 3.6 - - - pci-x 3.0 3.3 3.6 - - - a gp-1x 3.15 3.3 3.45 - - - sstl 2 2.3 2.5 2.7 1.15 1.25 1.35 sstl 3 3.0 3.3 3.6 1.3 1.5 1.7 ctt 3.3 3.0 3.3 3.6 1.35 1.5 1.65 ctt 2.5 2.3 2.5 2.7 1.35 1.5 1.65 hstl class i 1.4 1.5 1.6 0.68 0.75 0.9 hstl class iii 1.4 1.5 1.6 - 0.9 - hstl class iv 1.4 1.5 1.6 - 0.9 - gtl+ 1.4 - 3.6 0.882 1.0 1.122 l vpecl 3.0 3.3 3.6 - - - l vds 2.3 2.5/3.3 3.6 - - - blvds 2.3 2.5/3.3 3.6 - - - 1. inputs are independent of v cco setting. however, v cco must be set within the valid operating range for one of the supported standards. 2. software default setting.
lattice semiconductor ispgdx2 family data sheet 25 sysio single ended dc electrical characteristics over recommended operating conditions input/output standard v il v ih v ol max (v) v oh min (v) i ol 2 (ma) i oh 2 (ma) min (v) max (v) min (v) max (v) l vcmos 3.3 -0.3 0.8 2.0 5.5 0.4 2.4 20, 16, 12, 8, 5.33, 4 -20, -16, -12, -8, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 l vttl -0.3 0.8 2.0 5.5 0.4 2.4 4 -4 0.2 v cco - 0.2 0.1 -0.1 l vcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v cco - 0.4 16, 12, 8, 5.33, 4 -16, -12, -8, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 l vcmos 1.8 1, 3 -0.3 0.68 1.07 3.6 0.4 v cco - 0.4 8 -8 l vcmos 1.8 3 -0.3 0.68 1.07 3.6 0.4 v cco -0.4 12, 5.33, 4 -12, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 pci 3.3 4 -0.3 1.08 1.5 3.6 0.1 v cco 0.9 v cco 1.5 -0.5 pci -x 5 -0.3 1.26 1.5 3.6 0.1 v cco 0.9 v cco 1.5 -0.5 a gp-1x 4 -0.3 1.08 1.5 3.6 0.1 v cco 0.9 v cco 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v cco - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v cco - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v cco - 0.62 7.6 -7.6 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v cco - 0.43 15.2 -15.2 ctt 3.3 -0.3 v ref - 0.2 v ref + 0.2 3.6 v ref - 0.4 v ref + 0.4 8 -8 ctt 2.5 -0.3 v ref - 0.3 v ref + 0.2 3.6 v ref - 0.4 v ref + 0.4 8 -8 hstl class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v cco - 0.4 8 -8 hstl class iii -0.3 v ref - 0.2 v ref + 0.1 3.6 0.4 v cco - 0.4 24 -8 hstl class iv -0.3 v ref - 0.3 v ref + 0.1 3.6 0.4 v cco - 0.4 48 -8 gtl+ -0.3 v ref - 0.2 v ref + 0.2 3.6 0.6 n/a 36 n/a 1. software default setting. 2. the average dc current drawn by i/os between adjacent bank gnd connections, or between the last gnd in an i/o bank and the en d of the i/o bank, as shown in the logic signals connection table, shall not exceed n*8ma. where n is the number of i/os between ban k gnd connections or between the last gnd in a bank and the end of a bank. 3. for 1.8v devices (ispgdx2c) these speci cations are v il = 0.35 v cc and v ih = 0.65v cc 4. for 1.8v power supply devices these speci cations are v il = 0.3 * v cc * 3.3/1.8, v ih = 0.5 * v cc * 3.3/1.8 5. for 1.8v power supply devices these speci cations are v il = 0.35 * v cc * 3.3/1.8 and v ih = 0.5 * v cc * 3.3/1.8
lattice semiconductor ispgdx2 family data sheet 26 sysio differential dc electrical characteristics over recommended operating conditions l vpecl 1 figure 16. lvpecl driver with three resistor pack p arameter symbol parameter description test conditions min. typ. max. units l vds v inp v inm input voltage ? 0 ? 2.4 v v thd differential input threshold 0.2v v cm 1.8v +/-100 ? ? mv i in input current power on ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ? ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ? 0.9 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ? 250 350 450 mv ? v od change in v od between high and low ? ? ? 50 mv v os output voltage offset (v op - v om )/2, r t = 100 ? 1.125 1.25 1.375 v ? v os change in vos between h and l ? ? ? 50 mv i osd output short circuit current v od = 0v. driver outputs shorted. ??24 ma bus lvds 1 v oh output high voltage for v op or v om r t = 27 ? ? 1.4 1.80 v v ol output low voltage for v op or v om r t = 27 ? 0.95 1.1 ? v v od output voltage differential |v op - v om |, rt = 27 ? 240 300 460 mv ? v od change in v od between h and l ? ? 27 mv v os output voltage offset |v op - vom| /2, rt = 27 ? 1.1 1.3 1.5 v ? v os change in v os between h and l ? ? 27 mv i osd output short circuit current v od = 0. driver outputs shorted. ?3665ma 1. v op and v om are the two outputs of the lvds output buffer. dc parameter parameter description min. max. min. max. min. max. units v cco output supply voltage 3.0 3.3 3.6 v v ih input voltage high 1.49 2.72 1.49 2.72 1.49 2.72 v v il input voltage low 0.86 2.125 0.86 2.125 0.86 2.125 v v oh output voltage high 1.7 2.11 1.92 2.28 2.03 2.41 v v ol output voltage low 0.96 1.27 1.06 1.43 1.25 1.57 v v diff 2 differential input voltage 0.3 0.3 0.3 v 1. these values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see f igure 16). the v oh levels are 200mv below the standard lvpecl levels and are compatible with devices tolerant of the lower common mode ranges. 2. valid for 0.2v v cm 1.8v. zo zo rs r d a rs to lvpecl differential receiver 1/4 of bourns p/n cat 16-pc4f12 ispgdx2 lv p ecl buffer r t =100
lattice semiconductor ispgdx2 family data sheet 27 ispgdx2v/b/c, ispgdx2ev/eb/ec external switching characteristics over recommended operating conditions p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max. output paths t pd data from input pin to output pin ? 3.0 ? 3.2 ? 3.5 ? 5.0 ns t pd_sel data from global select pin to output pin ? 2.8 ? 3.0 ? 3.3 ? 4.7 ns t co global clock to output ? 2.9 ? 3.1 ? 3.2 ? 5.4 ns t ops set-up time before global clock 2.0 ? 2.0 ? 2.0 ? 3.0 ? ns t oph hold time after global clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t opces pt clock enable setup time before global clock 3.0 ? 3.0 ? 4.1 ? 6.9 ? ns t opceh pt clock enable hold time after global clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t oprsto external reset pin to output delay ? 5.3 ? 6.0 ? 6.0 ? 10.0 ns input paths t ips set-up time before global clock 0.5 ? 0.5 ? 0.5 ? 0.9 ? ns t ipsz set-up time before global clock (zero hold time) 2.0 ? 2.0 ? 2.0 ? 3.0 ? ns t iph hold time after global clock 1.0 ? 1.0 ? 1.0 ? 1.7 ? ns t iphz hold time after global clock (zero hold time) 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t ipces pt clock enable setup time before global clock 3.1 ? 3.1 ? 3.1 ? 5.1 ? ns t ipceh pt clock enable hold time after global clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t iprsto external reset pin to output delay ? 5.6 ? 6.5 ? 7.5 ? 12.5 ns output enable paths t oeco global clock to output enabled pin ? 4.2 ? 4.5 ? 5.5 ? 9.1 ns t oes output enable register set-up time before global clock 1.6 ? 1.6 ? 2.0 ? 3.4 ? ns t oeh hold time after global clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t oeces pt clock enable setup time before global clock 3.5 ? 3.5 ? 4.1 ? 6.9 ? ns t oeceh pt clock enable hold time after global clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t goe/dis global oe input to output enable/disable ? 3.5 ? 3.8 ? 4.5 ? 7.5 ns t t oe/dis t est oe input to output enable/disable ? 5.2 ? 5.5 ? 6.2 ? 10.3 ns t en/dis input to output enable/disable ? 5.2 ? 5.5 ? 6.2 ? 10.3 ns clock and reset paths t rw width of reset pulse 2.5 ? 2.5 ? 2.5 ? 4.1 ? ns t cw clock width 1.3 ? 1.5 ? 1.6 ? 2.7 ? ns t gw clock width 1.5 ? 1.6 ? 1.6 ? 2.7 ? ns f max (ext) clock frequency with external f eedback 1/(t ops + t co ) ?204?196? 192 ? 119 mhz f max (tog, no pll) clock frequency maximum toggle (no pll) ?360?330? 300 ? 180 mhz f max (tog, pll) clock frequency maximum toggle (with pll) ?360?330? 300 ? 180 mhz timing v.2.2
lattice semiconductor ispgdx2 family data sheet 28 timing model the task of determining the timing through the ispgdx2 family is relatively simple. the timing model provided in figure 17 shows the speci c delay paths. once the implementation of a given function is determined either con- ceptually or from the software report le, the delay path of the function can easily be determined from the timing model. the lattice design tools report the timing delays based on the same timing model for a particular design. note that the internal timing parameters are given for reference only, and are not tested. the external timing param- eters are tested and guaranteed for every device. figure 17. ispgdx2 timing model diagram (i/o cell) gsr t indio in oe reg. s/r ce dq t opbypass t ipbypass t routegrp to grp from grp t ptsel from grp from adjacent cells (output) t ptclken t ptclk from grp t oe bypas s t ptsr from grp output delays t buf t en t dis t ioo out t ptoe t oe path goe path from grp to adjacent cells (input) t opac italicized parameters are optional. model version 1.6.7 toe/ goe gsel t muxpd t muxsel t ioi t toe_in t goe_in t sr_in t ioi t sel_in t ioi t in t ioi to syshsi/fifo (sin, control, din, i/o reset, ssclkin) to syshsi (txd) to adjacent cells (output) to fifo (ren) to fifo (rclk) t clk_in t ioi t clken_in gclk/ gclken t gclk t pll_delay t pll_sec_delay to syshsi (refclk) to syshsi/fifo (global reset) from syshsi (ssclkout) t hsissclkout to fifo (wclk) to fifo (we) from syshsi/fifo (flags) t hsififoflag from syshsi (sout) t hsisout from adjacent cells (input) t ipac from fifo (dout) t fifodataout from syshsi (recclk, sydt) t hsiout from pll (pll output) t pllout output reg. input reg. s/r s/r ce ce d d q q
lattice semiconductor ispgdx2 family data sheet 29 figure 18. ispgdx2 timing model diagram (with syshsi and fifo receive mode) figure 19. ispgdx2 timing model diagram (with syshsi transmit mode) fifo t hsififorst read clock read enable write clk t fifowclk t fiforen t fiforclk syshsi (rxd) recovered clock full, empty to i/o cell (output path flags) from i/o cell (rclk) from i/o cell (re) reset reset hsi controls hsi flags cslock to i/o cell (output path flag) sydt to i/o cell (sydt and output path flags) serial data in t hsisin from i/o cell (sin) data in t fifodatain data out (rxd) from i/o cell (control) cal t hsictrlcal to i/o cell (recclk) data out to i/o cell (dout) fifo flags from i/o cell (global reset) from i/o cell (i/o reset) reference clock t hsirefclk from i/o cell (refclk) source synchronous clock t hsissclkin from i/o cell (ssclkin) syshsi (txd) serial data out to i/o cell (sout) data in t hsitxdata from i/o cell (txd) reference clock t hsirefclk from i/o cell (refclk) source synchronous clock to i/o cell (ssclkout)
lattice semiconductor ispgdx2 family data sheet 30 figure 20. ispgdx2 timing model diagram (in fifo only mode) fifo data in data out t hsififorst read clock read enable write clock write enable t fifowen t fifowclk t fifodatain to i/o cell (dout) full, empty reset from i/o cell (din) from i/o cell (wclk) from i/o cell (we) t fiforen t fiforclk from i/o cell (rclk) from i/o cell (re) from i/o cell (global reset) from i/o cell (i/o reset) to i/o cell (output path flags) fifo flags
lattice semiconductor ispgdx2 family data sheet 31 sample external timing calculations the following equations illustrate the task of determining the timing through the ispgdx2 family. these are only a sample of equations to calculate the timing through the ispgdx2. figure 17 shows the speci c delay paths and the internal timing parameters table provides the parameter values. note that the internal timing parameters are given for reference only and are not tested. the external timing param- eters are tested and guaranteed for every device. data from global select pin to output pin: t pd_sel = t sel_in + t muxsel + t opbypass + t buf global clock to output: t co = t clk_in + t gclk + t opcoi + t buf input register or latch set-up time before global clock: t ips = t in + t ips - (t clk + t gclk ) input register or latch hold time after global clock: t iph = (t clk_in + t gclk ) + t iphi - t in data from product term select to output pin: t pd_ptsel = t in + t ipbypass + t r outegrp + t ptsel + t muxsel + t opbypass + t buf product term clock to output: t co_pt = t in + t ipbypass + t r outegrp + t ptclk + t opcoi + t buf input register or latch set-up time before product term clock: t ips_pt = t in + t ipsi_pt - (t in + t ipbypass + t r outegrp + t ptclk ) input register or latch hold time after product term clock: t iph_pt = (t in + t ipbypass + t r outegrp + t ptclk ) + t iphi - t in global oe input to output enable/disable: t goe/dis = t goe_in + t oebypass + t en external reset pin to output delay: t oprsto = t sr_in + t opasroi + t buf
lattice semiconductor ispgdx2 family data sheet 32 ispgdx2v/b/c, ispgdx2ev/eb/ec internal timing parameters 1 over recommended operating conditions p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max. input/output delays t buf output buffer delay ? 0.80 ? 0.80 ? 0.80 ? 1.14 ns t clk_in global clock input delay ? 1.00 ? 1.00 ? 1.00 ? 1.67 ns t clken_in global clock enable input delay ? 1.80 ? 1.80 ? 1.80 ? 3.00 ns t dis output disable delay ? 1.80 ? 1.80 ? 2.50 ? 4.17 ns t en output enable delay ? 1.50 ? 1.80 ? 2.50 ? 4.17 ns t goe_in global output enable path delay ? 2.00 ? 2.00 ? 2.00 ? 3.33 ns t in input pin delay ? 0.40 ? 0.40 ? 0.40 ? 0.57 ns t sel_in global mux select input delay ? 1.60 ? 1.60 ? 1.60 ? 2.29 ns t sr_in global set/reset path delay ? 2.00 ? 2.70 ? 2.70 ? 4.50 ns t t oe_in t est output enable path delay ? 3.70 ? 3.70 ? 3.70 ? 6.17 ns shift register and mux delays t ipac input path adjacent i/o cell delay (shift register) ? 0.80 ? 0.80 ? 0.80 ? 1.33 ns t opac output path adjacent i/o cell delay (shift register) ? 1.30 ? 1.30 ? 1.30 ? 2.17 ns t muxpd mux data path delay ? 0.90 ? 0.90 ? 0.90 ? 1.29 ns t muxsel mux select path delay ? 0.40 ? 0.40 ? 0.40 ? 0.57 ns and arrays and routing delays t fifodataout fifo output to i/o block delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t gclk clock tree delay ? 0.40 ? 0.40 ? 0.40 ? 0.67 ns t hsififoflag hsi/fifo flag to i/o block delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t hsiout hsi output to i/o cell block delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t hsissclkout hsi source synchronous clock to i/o cell block delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t pll_delay pll delay increment ? 0.33 ? 0.33 ? 0.33 ? 0.33 ns t ptclk clock and array delay ? 2.20 ? 2.20 ? 2.20 ? 3.67 ns t ptclken clock enable and array delay ? 2.10 ? 2.10 ? 2.10 ? 3.50 ns t ptoe oe and array delay ? 2.40 ? 2.40 ? 2.40 ? 4.00 ns t ptsel select and array delay ? 1.70 ? 1.70 ? 1.70 ? 2.83 ns t ptsr set/reset and array delay ? 1.40 ? 1.40 ? 2.70 ? 4.50 ns t r outegrp global routing pool delay ? 0.90 ? 0.90 ? 0.90 ? 1.29 ns register/latch delays, output paths t opasroi asynchronous set/reset to output ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns t opasrri asynchronous set/reset recovery ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns t opbypass register/latch bypass delay ? 0.00 ? 0.20 ? 0.50 ? 0.71 ns t opcehi register clock enable hold time 1.30 ? 1.30 ? 1.30 ? 2.17 ? ns t opcesi register clock enable setup time (global clock enable) 1.10 ? 1.10 ? 1.10 ? 1.83 ? ns t opcesi_pt register clock enable setup time (product term clock enable) 1.00 ? 1.00 ? 2.10 ? 3.50 ? ns t opcoi register clock to output delay ? 0.70 ? 0.90 ? 1.00 ? 1.67 ns t ophi register hold time 0.80 ? 0.80 ? 0.80 ? 1.33 ? ns
lattice semiconductor ispgdx2 family data sheet 33 t oplgoi latch gate to output delay ? 1.00 ? 1.00 ? 1.00 ? 1.67 ns t oplhi latch hold time 0.80 ? 0.80 ? 0.80 ? 1.33 ? ns t oplpdi latch propagation delay (transparent mode) ? 0.30 ? 0.30 ? 0.30 ? 0.50 ns t oplsi latch setup time (global gate) 1.20 ? 1.20 ? 1.20 ? 2.00 ? ns t oplsi_pt latch setup time (product term gate) 1.00 ? 1.00 ? 1.00 ? 1.67 ? ns t opsi register setup time (global clock) 1.20 ? 1.20 ? 1.20 ? 2.00 ? ns t opsi_pt register setup time (product term clock) 1.00 ? 1.00 ? 1.00 ? 1.67 ? ns t opsrpwi asynchronous set/reset pulse width ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns register/latch delays, input paths t ipasroi asynchronous set/reset to output ? 1.00 ? 1.00 ? 1.70 ? 2.83 ns t ipasrri asynchronous set/reset recovery ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns t ipbypass register/latch bypass delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t ipcehi register clock enable hold time 1.30 ? 1.30 ? 1.30 ? 2.17 ? ns t ipcesi register clock enable setup time (global clock enable) 1.10 ? 1.10 ? 1.10 ? 1.83 ? ns t ipcesi_pt register clock enable setup time (product term clock enable) 1.10 ? 1.10 ? 1.10 ? 1.83 ? ns t ipcoi register clock to output delay ? 0.80 ? 1.00 ? 1.00 ? 1.67 ns t iphi register hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t iplgoi latch gate to output delay ? 1.00 ? 1.00 ? 1.00 ? 1.67 ns t iplhi latch hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t iplpdi latch propagation delay (transparent mode) ? 0.30 ? 0.30 ? 0.30 ? 0.50 ns t iplsi latch setup time (global term) 1.50 ? 1.50 ? 1.50 ? 2.50 ? ns t iplsi_pt latch setup time (product term gate) 1.50 ? 1.50 ? 1.50 ? 2.50 ? ns t ipsi register setup time (global clock) 1.50 ? 1.50 ? 1.50 ? 2.50 ? ns t ipsi_pt register setup time (product term clock) 1.50 ? 1.50 ? 1.50 ? 2.50 ? ns t ipsrpwi asynchronous set/reset pulse width ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns oe paths t oeasroi asynchronous set/reset to output ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns t oeasrri asynchronous set/reset recovery ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns t oebypass register/latch bypass delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t oecehi register clock enable hold time 1.30 ? 1.30 ? 0.80 ? 1.33 ? ns t oecesi register clock enable setup time (global clock enable) 1.20 ? 1.20 ? 1.20 ? 2.00 ? ns t oecesi_pt register clock enable setup time (product term clock enable) 1.50 ? 1.50 ? 2.10 ? 3.50 ? ns t oecoi register clock to output delay ? 1.30 ? 1.30 ? 1.60 ? 2.67 ns t oehi register hold time 0.40 ? 0.40 ? 0.40 ? 0.67 ? ns t oelgoi latch gate to output delay ? 1.60 ? 1.60 ? 1.60 ? 2.67 ns t oelhi latch hold time 0.40 ? 0.40 ? 0.40 ? 0.67 ? ns t oelpdi latch propagation delay (transparent mode) ? 0.30 ? 0.30 ? 0.30 ? 0.50 ns ispgdx2v/b/c, ispgdx2ev/eb/ec internal timing parameters 1 (continued) over recommended operating conditions p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max.
lattice semiconductor ispgdx2 family data sheet 34 t oelsi latch setup time (global gate) 1.40 ? 1.40 ? 1.40 ? 2.33 ? ns t oelsi_pt latch setup time (product term gate) 1.00 ? 1.00 ? 1.00 ? 1.67 ? ns t oesi register setup time (global clock) 1.00 ? 1.00 ? 1.40 ? 2.33 ? ns t oesi_pt register setup time (product term clock) 1.00 ? 1.00 ? 1.00 ? 1.67 ? ns t oesrpwi asynchronous set/reset pulse width ? 2.50 ? 2.50 ? 2.50 ? 4.17 ns timing v.2.2 1. internal parameters are not tested and are for reference only. refer to the timing model in this data sheet for details. 2. t pll_delay is the unit of increment by which the clock signal can be incremented. the pll can adjust the clock signal by up to t range (as given in the sysclock pll timing section) in either direction in steps of size t pll_delay. ispgdx2v/b/c, ispgdx2ev/eb/ec internal timing parameters 1 (continued) over recommended operating conditions p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max.
lattice semiconductor ispgdx2 family data sheet 35 ispgdx2v/b/c, ispgdx2ev/eb/ec timing adjusters p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max. optional adders t indio input delay ? 1.50 ? 1.50 ? 1.50 ? 2.50 ns t pll_sec_delay secondary pll output delay ? 1.30 ? 1.30 ? 1.30 ? 1.30 ns t ioo output adjusters slow slew using slow slew (lvttl and l vcmos outputs only) ? 0.90 ? 0.90 ? 0.90 ? 0.90 ns l vttl_out using 3.3v ttl drive ? 1.20 ? 1.20 ? 1.20 ? 1.20 ns l vcmos_18_4ma_out using 1.8v cmos standard, 4ma drive ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns l vcmos_18_5.33ma_out using 1.8v cmos standard, 5.33ma drive ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns l vcmos_18_8ma_out using 1.8v cmos standard, 8ma drive ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vcmos_18_12ma_out using 1.8v cmos standard, 12ma drive ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vcmos_25_4ma_out using 2.5v cmos standard, 4ma drive ? 1.20 ? 1.20 ? 1.20 ? 1.20 ns l vcmos_25_5.33ma_out using 2.5v cmos standard, 5.33ma drive ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns l vcmos_25_8ma_out using 2.5v cmos standard, 8ma drive ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns l vcmos_25_12ma_out using 2.5v cmos standard, 12ma drive ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns l vcmos_25_16ma_out using 2.5v cmos standard, 16ma drive ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns l vcmos_33_4ma_out using 3.3v cmos standard, 4ma drive ? 1.20 ? 1.20 ? 1.20 ? 1.20 ns l vcmos_33_5.33ma_out using 3.3v cmos standard, 5.33ma drive ? 1.20 ? 1.20 ? 1.20 ? 1.20 ns l vcmos_33_8ma_out using 3.3v cmos standard, 8ma drive ? 0.80 ? 0.80 ? 0.80 ? 0.80 ns l vcmos_33_12ma_out using 3.3v cmos standard, 12ma drive ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vcmos_33_16ma_out using 3.3v cmos standard, 16ma drive ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vcmos_33_20ma_out using 3.3v cmos standard, 20ma drive ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns a gp_1x_out using agp 1x standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns blvds_out using bus low voltage dif- f erential signaling (blvds) ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns ctt25_out using ctt 2.5v ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns ctt33_out using ctt 3.3v ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns gtl+_out using gtl+ ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns hstl_i_out using hstl 2.5v, class i ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns hstl_iii_out using hstl 2.5v, class iii ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns hstl_iv_out using hstl 2.5v, class iv ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns
lattice semiconductor ispgdx2 family data sheet 36 l vpecl_out using lvpecl differential signaling ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns l vds_out using low voltage differen- tial signaling (lvds) ? 0.80 ? 0.80 ? 0.80 ? 0.80 ns pci_out using pci standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns pci_x_out using pci-x standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns sstl2_i_out using sstl 2.5v, class i ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns sstl2_ii_out using sstl 2.5v, class ii ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns sstl3_i_out using sstl 3.3v, class i ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns sstl3_ii_out using sstl 3.3v, class ii ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns t ioi input adjusters l vttl_in using 3.3v ttl ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vcmos_18_in using 1.8v cmos ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vcmos_25_in using 2.5v cmos ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vcmos_33_in using 3.3v cmos ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns a gp_1x_in using agp 1x ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns blvds_in using bus low voltage differ- ential signaling (blvds) ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns ctt25_in using ctt 2.5v ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns ctt33_in using ctt 3.3v ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns gtl+_in using gtl+ ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns hstl_i_in using hstl 2.5v, class i ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns hstl_iii_in using hstl 2.5v, class iii ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns hstl_iv_in using hstl 2.5v, class iv ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vpecl_in using differential signaling (lvpecl) ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns l vds_in using low voltage differen- tial signaling (lvds) ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns pci_in using pci ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns pci_x_in using pci-x ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl2_i_in using sstl 2.5v, class i ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns sstl2_ii_in using sstl 2.5v, class ii ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns sstl3_i_in using sstl 3.3v, class i ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns sstl3_ii_in using sstl 3.3v, class ii ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns timing v.2.2 ispgdx2v/b/c, ispgdx2ev/eb/ec timing adjusters (continued) p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max.
lattice semiconductor ispgdx2 family data sheet 37 ispgdx2v/b/c, ispgdx2ev/eb/ec fifo internal timing p arameter description -3 -32 -35 -5 units min. max. min. max. min. max. min. max. routing delays t fifodatain fifo input delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifodataout fifo output to i/o core delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fiforclk read clock input delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fiforen read clock enable input delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifowclk write clock input delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifowen write clock enable input delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns core delays t fifoclkskew global read clock to write clock skew ? 2.00 ? 2.00 ? 2.00 ? 3.33 ns t fifoempty read clock to empty flag delay ? 1.30 ? 1.80 ? 1.80 ? 3.00 ns t fifofull write clock to full flag delay ? 1.30 ? 1.80 ? 1.80 ? 3.00 ns t fiforceh read clock hold after read clock enable time ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fiforces read clock setup before read clock enable time ? 1.50 ? 1.50 ? 1.50 ? 2.50 ns t fiforclko read clock to fifo out delay ? 0.50 ? 0.50 ? 0.50 ? 0.83 ns t fiforsto reset to output delay ? 0.70 ? 0.70 ? 0.70 ? 1.17 ns t fiforstpw reset pulse width ? 2.00 ? 2.00 ? 2.00 ? 3.33 ns t fiforstr reset recovery time ? 1.20 ? 1.50 ? 2.00 ? 3.33 ns t fifostrd write clock to start read flag delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifothru flow through delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifowceh write clock hold after write clock enable time ? 2.00 ? 2.00 ? 2.00 ? 3.33 ns t fifowces write clock setup before write clock enable time ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t fifowclkh write data hold after write clock time ? 0.50 ? 0.50 ? 0.70 ? 1.17 ns t fifowclks write data setup before write clock time ? 1.00 ? 1.00 ? 1.00 ? 1.67 ns timing v.2.2
lattice semiconductor ispgdx2 family data sheet 38 syshsi block timing figure 21 provides a graphical representation of the serdes receiver input requirements. it provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and p and n input skew tolerance. figure 21. receive data eye diagram template (differential) the data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal quality. almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye closure. this combined with the eye-opening limitations of the line receiver can provide a good indication of a link?s ability to transfer error-free data. signal jitter is of special interest to system designers. it is often the primary limiting characteristic of long digital links and of systems with high noise level environments. an interesting characteristic of the clock and data recovery (cdr) portion of the ispgdx2 serdes receiver is its ability to lter incoming signal jitter that is below the clock recovery pll bandwidth. for signals with high levels of low frequency jitter, the receiver can detect incoming data error free, with eye openings signi cantly less than that shown in figure 21. syshsi block ac speci cations operating frequency ranges symbol description mode test condition min. max. units f clk reference clock frequency ss:cal 50 200 mhz 10b12b 33 67 mhz 8b10b 40 80 mhz f sin 2 serial input ss:cal with eo sin 400 800 1 mbps 10b12b with eo sin 400 800 1 mbps 8b10b with eo sin 400 800 1 mbps f sout 2 serial out lvds c l = 5 pf, r l = 100 ohms, f clk with no jitter 400 800 1 mbps 1. f sin (8b/10b and 10b/12b) 800mbps limit applicable only to the fastest speed grade. limit is 700mbps for the lower speed grade. 2. f sin and f sout speeds are supported at v cc and v ccp at 1.7v to 1.9v for ispgdx2c devices. eo sin v thd 200 mv differential +/- 100 mv single ended jt th bit time jt th : optimum threshold crossing jitter jt th
lattice semiconductor ispgdx2 family data sheet 39 lockin time refclk and ss_clkin timing serializer timing 2 symbol description mode condition min. max. units t sclock cspll lock time all after input is stabilized 25 s t cdrlock cdrpll lock-in time ss with ss mode sync pattern 1024 t rcp 1 10b12b with 10b12b sync pattern 1024 t rcp 8b10b with 8b10b idle pattern 960 t rcp t sync syncpat length ss 1200 t rcp t cal cal duration ss 1100 t rcp t susync syncpat set-up time to cal ss 50 t rcp t hdsync syncpat hold time from cal ss 50 t rcp 1. refclk clock period. symbol description mode condition min. max. units t drefclk f requency deviation between tx refclk and cdrx refclk on one link 8b10b/ 10b12b -100 100 ppm t jpprefclk refclk, ss_clkin peak-to-peak period jitter all random jitter 0.01 uipp t pwrefclk refclk, ss_clkin pulse width, (80% to 80% or 20% to 20%). all 1 ns t rfrefclk refclk, ss_clkin rise/fall time (20% to 80% or 80% to 20%) all 2 ns symbol description mode condition min. max. units t jppsout sout peak-to-peak output data jitter all f clk with no jitter 0.25 uipp t jpp8b10b sout peak-to-peak random jitter 8b10b 800 mbps w/k28.7- 130 ps sout peak-to-peak deterministic jitter 8b10b 800 mbps w/k28.5+ 160 ps t rfsout sout output data rise/fall time (20%, 80%) l vds 700 ps blvds 900 ps t cosout refclk to sout delay ss/8b10b 2bt 1 + 2 2bt 1 +10 ns 10b12b 1bt 1 + 2 1bt 1 +10 ns t sktx skew of sout with respect to ss_clkout ss 250 ps t ckosout ss_clkout to bit0 of sout ss 2bt 1 - t sktx 2bt 1 + t sktx ns t hsitxddatas txd data setup time all note 3 1.5 ns t hsitxddatah txd data hold time all note 3 1.0 ns 1. bt: bit time period. high speed serial bit time. 2. the sin and sout jitter speci cations listed above are under the condition that the clock tree that drives the refclk to syshsi block is in sysclock pll bypass mode. 3. internal timing for reference only.
lattice semiconductor ispgdx2 family data sheet 40 deserializer timing lock-in timing symbol description mode conditions min. max. units f dsin sin frequency deviation from refclk 8b10b/ 10b12b -100 100 ppm eo sin sin eye opening tolerance all notes 1, 2 0.45 uipp ber bit error rate all 10 -12 bits t hsioutvalidpre rxd, sydt valid time before recclk fall- ing edge all note 3 t rcp /2 - 0.7 ns t hsioutvalidpost rxd, sydt valid time after recclk falling edge all note 3 t rcp /2 - 0.7 ns t dsin bit 0 of sin delay to rxd valid at recclk f alling edge all 1.5 t rcp + 4.5bt + 2 1.5 t rcp + 4.5bt + 10 ns 1. eye opening based on jitter frequency of 100khz. 2. lower frequency operation assumes maximum eye closure of 800ps. 3. internal timing for reference only. training sequence ss mode data transfer sin cal sydt rxd(0:7) cdrx_ss lock-in (de-skew) timin g data (serial) min. 1200 syncpat min. 1100 ls cycl e syncpat data (parallel) t susync t hdsync sin sydt rxd(0:9) cdr_10b12b lock-in timin g data (serial) 1024 syncpat syncpat data (parallel)
lattice semiconductor ispgdx2 family data sheet 41 lock-in timing (continued) sydt timing si sydt n rxd(0:9) cdr_8b10b lock-in timing data (serial) 240 idle pattern(960 trcp) idle pattern data (parallel) recclk sydt rxd(0:9) sydt timing for cdrx_10b12b sync pattern data0 data1 data2 parallel data data3 data4 recclk sydt rxd(0:9) sydt timing for cdrx_8b10b k28.5 d21.4 d21.5 d21.5 k28.5 d21.4 d21.5 d21.5 idle pattern idle pattern d0 d1 d2 data
lattice semiconductor ispgdx2 family data sheet 42 serializer timing 8b/10b serializer delay timing txd refclk sout t cosout symbol n symbol n+1 symbol n symbol n-1 symbol n+1 b9 b0 b1 b2 b5 b6 b7 b8 b3 b4 b5 b4 b1 b2 b7 b8 b9 b0 b6 symbol n symbol n+1 10b/12b serializer delay timing txd refclk sout t cosout symbol n symbol n-1 b9 b0 b1 b2 b5 b6 b7 b8 b3 b4 b5 b4 b7 b8 b9 b6 "0" "1" "0" "1" ss mode serializer delay timing txd refclk sout symbol n symbol n+1 symbol n symbol n-1 symbol n+1 b0 b1 b2 b5 b6 b7 b3 b4 b5 b4 b7 b6 b0 ss_clkout t cosout t sktx t ckosout t hsitxddatas t hsitxddatah internal timing for syshsi block refclk txd t pwrefclk
lattice semiconductor ispgdx2 family data sheet 43 deserializer timing 10b/12b deserializer delay timing sin rxd recclk t tdsin symbol n+1 symbol n b0 b1 b2 b5 b3 b4 b5 b4 b7 b8 b9 b6 "1" "0" "1" b0 b 1b2 b3 b7 b8 b9 b6 b4 "0" "1" b0 b1 b2 b3 symbol n- 1 symbol n-2 symbol n symbol n+2 cdrx_ss deserializer delay timing rxd recclk sin t dsin symbol n+1 symbol n b1 b2 b3 b5 b5 b6 b7 b0 b6 b7 b0 b4 b1 b2 b2 b3 b4 b0 b1 b3 symbol n+2 b4 symbol n-2 symbol n-1 symbol n 8b/10b deserializer delay timing rxd recclk sin t dsin symbol n+1 symbol n b9 b0 b1 b2 b5 b6 b7 b8 b3 b4 b5 b4 b1 b2 b7 b8 b9 b0 b6 b3 b4 b1 b2 b0 b3 symbol n+ 2 b5 symbol n-1 symbol n t hsioutvalidpost t hsioutvalidpre recclk internal timing for syshsi block sydt, rxd
lattice semiconductor ispgdx2 family data sheet 44 sysclock pll timing over recommended operating conditions symbol parameter conditions min max units t pwh input clock, high time 80% to 80% 0.5 ? ns t pwl input clock, low time 20% to 20% 0.5 ? ns t r , t f input clock, rise and fall time 20% to 80% ? 3.0 ns t instb input clock stability, cycle to cycle (peak) ? +/- 300 ps f mdivin m divider input, frequency range 10 320 mhz f mdivout m divider output, frequency range 10 320 mhz f ndivin n divider input, frequency range 10 320 mhz f ndivout n divider output, frequency range 10 320 mhz f vdivin v divider input, frequency range 100 400 mhz f vdivout v divider output, frequency range 10 320 mhz t outduty output clock, duty cycle 40 60 % t jit(cc) output clock, cycle to cycle jitter (peak) clean reference 1 : 10 mhz f mdivout 40 mhz or 100 mhz f vdivin 160 mhz ? +/- 600 ps clean reference 1 : 40 mhz f mdivout 320 mhz and 160 mhz f vdivin 400 mhz ? +/- 150 ps t jit(period) 2 output clock, period jitter (peak) clean reference 1 : 10 mhz f mdivout 40 mhz or 100 mhz f vdivin 160 mhz ? +/- 600 ps clean reference 1 : 40 mhz f mdivout 320 mhz and 160 mhz f vdivin 400 mhz ? +/- 150 ps t clk_out_dly input clock to clk_out delay internal feedback ? 3.4 ns t phase input clock to external feedback delta external feedback ? 500 ps t lock time to acquire phase lock after input stable ? 25 us t pll_delay delay increment (lead/lag) typical = +/- 250ps +/- 120 +/- 550 ps t range t otal output delay range (lead/lag) +/- 0.84 +/- 3.85 ns t pll_rstw minimum reset pulse width 1.8 ? ns 1. this condition assures that the output phase jitter will remain within speci cation. jitter speci cation is based on optimized m, n and v set- tings determined by the isplever software. 2. accumulated jitter measured over 10,000 waveform samples
lattice semiconductor ispgdx2 family data sheet 45 boundary scan timing speci cations over recommended operating conditions p arameter description min max units t btcp tck [bscan] clock pulse width 40 ? ns t btcph tck [bscan] clock pulse width high 20 ? ns t btcpl tck [bscan] clock pulse width low 20 ? ns t bts tck [bscan] setup time 8 ? ns t bth tck [bscan] hold time 10 ? ns t btrf tck [bscan] rise/fall time 50 ? mv/ns t btco t ap controller falling edge of clock to valid output ? 10 ns t btcodis t ap controller falling edge of clock to valid disable ? 10 ns t btcoen t ap controller falling edge of clock to valid enable ? 10 ns t btcrs bscan test capture register setup time 8 ? ns t btcrh bscan test capture register hold time 10 ? ns t b utco bscan test update register, falling edge of clock to valid output ? 25 ns t btuodis bscan test update register, falling edge of clock to valid disable ? 25 ns t btupoen bscan test update register, falling edge of clock to valid enable ? 25 ns
lattice semiconductor ispgdx2 family data sheet 46 po wer consumption po wer estimation coef cients ? core and pll i dc : blank chip background current k ref : reference voltage circuit current per bank k in : i/o current per input per mhz k core : core current per mhz with grp fanout of 1 k plld : pll logic current per mhz per pll k plla : pll analog portion current per mhz per pll po wer estimation coef cients ? syshsi k rxd : receiver logic current per mbps k rxstby : receiver logic standby current k rxa : receiver analog portion current per mbps k txd : tr ansmitter logic current per mbps k txstby : tr ansmitter logic standby current k txa : tr ansmitter analog portion current per mbps device v cc i dc (ma) k ref k in k core k plld k plla ispgdx2-256 3.3 10.0 3.25 0.0139 0.292 0.157 0.024 2.5 10.0 3.13 0.0139 0.292 0.157 0.024 1.8 4.0 3.00 0.0213 0.239 0.179 0.024 device v cc k rxd k rxstby k rxa k txd k txstby k txa ispgdx2-256 3.3 0.027 1.3 0.0023 0.011 2.4 0.0018 2.5 0.027 1.3 0.0023 0.011 2.4 0.0018 1.8 0.019 3.7 0.0040 0.011 1.2 0.0023 0 50 100 150 200 050100 150 200 250 300 350 0 10 20 30 40 50 60 70 80 90 0200 400 600 800 1000 1200 i core mhz ma ma ma mbps mhz i hsi i pll i pll_d i hsi_d i hsi_a i pll_a 0 20 40 60 80 100 0 200 400 600
lattice semiconductor ispgdx2 family data sheet 47 po wer consumption (continued) po w er consumption in the ispgdx2 family is the sum of three components: i cc-total = i core + i pll + i hsi (i cc-total combines current supplied via v cc pins and v ccp pins) i core =i dc + i ref + i in = blank chip background current + k ref * number of banks with v ref active + (k in * number of inputs + k core ) * average input switching frequency (mhz) i pll =i pll_d + i pll_a =[k plld * f vco * number of plls used] + [k plla * f vco * number of plls used] = [(k plld + k plla ) * f vco ] * number of plls used i hsi =i rx + i tx = [(k rxd + k rxa ) * f rx + i rxstby ] * number of receiver channels + [(k txd + k txa ) * f tx + i txstby ] * number of transmitter channels where: f vco : sysclock pll vco frequency in mhz f rx : syshsi receiver serial data rate f tx : syshsi transmitter serial data rate i hsi can also be determined by calculating i hsi_d , the current supplied by the v cc pin, and i hsi_a, the current sup- plied by the v ccp0 and v ccp1 . i hsi =i hsi_d + i hsi_a = [(k rxd * f rx + i rxstby )* number of receiver channels + (k txd * f tx + i txstby ) * number of transmitter channels] +[(k rxa * f rx ) * number of receiver channels + (k txa * f tx ) * number of transmitter channels] the i ccp is supplied through v ccp0 and v ccp1 pins for pll and syshsi analog portion. the equation for i ccp can be derived from the equations below. i ccp =i pll_a + i hsi_a = [(k plla * f vco ) * number of plls used] + [(k rxa * f rx ) * number of receiver channels + (k txa * f tx ) * number of transmitter channels] where: i pll_a : pll analog portion current i hsi_a : hsi analog portion current note: for further information about the use of these coef cients, refer to technical note tn1034, po w er estimation in the ispgdx2 family. i cc-total estimates are based on typical conditions. these values are for estimates only. since the value of i cc- total is sensitive to operating conditions and the program in the device, the actual current should be veri ed.
lattice semiconductor ispgdx2 family data sheet 48 switching test conditions figure 22 shows the output test load used for ac testing. speci c values for resistance, capacitance, voltage and other test conditions are shown in table 7. figure 22. output test load, lvttl and lvcmos standards (1.8v) ta b le 7. test fixture required components t est condition r 1 r 2 c l timing ref. v cco default lvcmos 1.8 i/o (l -> h, h -> l) 106 106 35pf v cco /2 1.8v l vcmos i/o (l -> h, h -> l) ? ? 35pf l vcmos3.3 = 1.5v lvcmos3.3 = 3.0v l vcmos2.5 = v cco /2 lvcmos2.5 = 2.3v l vcmos1.8 = v cco /2 lvcmos1.8 = 1.65v default lvcmos 1.8 i/o (z -> h) ? 106 35pf v cco /2 1.65v default lvcmos 1.8 i/o (z -> l) 106 ? 35pf v cco /2 1.65v default lvcmos 1.8 i/o (h -> z) ? 106 5pf v oh - 0.15 1.65v default lvcmos 1.8 i/o (l -> z) 106 ? 5pf v ol + 0.15 1.65v note: output test conditions for all other interfaces are determined by the respective standards. v cco r 1 r 2 c l * device output test poin t *c l includes test fixture and probe capacitance.
lattice semiconductor ispgdx2 family data sheet 49 signal descriptions 1 signal names description general purpose bkx_ioy input/output ? general purpose i/o number y in i/o bank x. gclk/ce0, gclk/ce1, gclk/ce2, gclk/ce3 input ? global clock/clock enable inputs. sel0, sel1, sel2 2 , sel3 2 input ? global mux select inputs. goe0, goe1, goe2 2 , goe3 2 input ? global output enable inputs. resetb input ? global reset signal (active low). nc no connect. gnd gnd ? ground. v cc vcc ? the power supply pins for core logic. v ccj vcc ? the power supply for the jtag logic. v cco x vcc ? the power supply pins for i/o bank x. v ref x input ? de nes the reference voltage for i/o bank x. t esting and programming tms input ? test mode select input, used to control the 1149.1 state machine. tck input ? test clock input pin, used to clock the 1149.1 state machine. tdi input ? test data in pin, used to load data into device using 1149.1 state machine. tdo output ? test data out pin used to shift data out of device using 1149.1. to e input ? test output enable pin. toe tristates all i/o pins when driven low. pll functions pll_fbkz input ? optional feedback input allows external feedback for pll z. pll_rstz input ? optional input resets the m divider in pll z. clk_outz output ? optional clock output from pll z (clock signal occupies the input path of this i/o pad). pll_lockz output ? optional lock output from pll z (lock signal occupies the input path of this i/o pad). gnd p0, gnd p1 gnd ? ground for plls. v ccp0, v ccp1 vcc ? the power supply pins for plls. fifo functions fifoy_din w input ? data in bit w of fifo y. fifoy_dout w internal signal ? data out bit w of fifo y fifoy_fiforstb input ? reset input for fifo y (active low). fifoy_full output ? full ag for fifo y. fifoy_empty output ? empty ag for fifo y. fifoy_strdb output ? start read (strdb) ag for fifo y. serdes functions hsima_sinp, hsimb_sinp input ? positive sense serial input for syshsi block m channel a, b. hsima_sinn, hsimb_sinn input ? negative (minus) sense serial input for syshsi block m channel a, b. hsima_soutp, hsimb_soutp output ? positive sense serial output for syshsi block m channel a, b. hsima_soutn, hsimb_soutn output ? negative (minus) sense serial output for syshsi block m channel a, b. hsima_sydt, hsimb_ sydt output ? symbol alignment detect for syshsi block m channel a, b. hsima_recclk, hsimb_recclk internal signal ? recovered clock for syshsi block m channel a, b. hsima_cdrrstb, hsimb_cdrrstb input ? resets the cdr circuit of syshsi block m channel a, b. hsim_cslock output ? lock output of the pll associated with channel m.
lattice semiconductor ispgdx2 family data sheet 50 ispgdx2-64 power supply and nc connections 1 hsima_txdw, hsimb_ txd w internal signal ? parallel data in bit w for syshsi block m channel a, b. hsima_rxdw, hsimb_ rxd w internal signal ? parallel data out bit w for syshsi block m channel a, b. source synchronous functions ss_sclkin0p, ss_sclkin1p input ? positive sense clock input for source synchronous group a, b. ss_sclkin0n, ss_sclkin1n input ? negative (minus) sense clock input for source synchronous group a, b. ss_clkout0n, ss_clkout1p output ? positive sense clock output for source synchronous group a, b. ss_clkout0n, ss_clkout1n output ? negative (minus) sense clock output for source synchronous group a, b. cal input ? initiates source synchronous calibration sequence. 1. m, w, x, y and z are variables. 2. not on ispgdx2-64 signal ispgdx2-64 (100-ball fpbga) 2 v cc a1, k10 v cco0 j7 v cco1 f10 v cco2 e10 v cco3 b7 v cco4 b4 v cco5 e1 v cco6 f1 v cco7 k4 v ccj k1 v ccp0 g6 gnd p0 g5 gnd a10, b9, c8, e6, e5, f6, f5, h3, j2 1. all grounds must be electrically connected at the board level. 2. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and n umerical order ascending horizontally. signal descriptions 1 (continued) signal names description
lattice semiconductor ispgdx2 family data sheet 51 ispgdx2 power supply and nc connections 1 signal ispgdx2-128 (208-ball fpbga) 3 ispgdx2-256 (484-ball fpbga) 3 v cc b15, c14, r15, b2, c3, p3, r2, aa3, aa20, b3, b20, c2, c11, c12, c21, h9, h10, h11, h12, h13, h14, j8, j15, k8, k15, l8, l15, l20, m3, m8, m15, m20, n8, n15, p8, p15, r9, r10, r11, r12, r13, r14, y2, y11, y12, y21 v cco0 n11, t12 aa14, ab20, y17 v cco1 l13, m16 p21, u20, y22 v cco2 e16, f13 c22, e20, j21 v cco3 a12, d11 a20, b14, c17 v cco4 a5, d6 a3, b9, c6 v cco5 e1, f4 c1, f3, j2 v cco6 l4, m1 p2, u3, y1 v cco7 n6, t5 aa9, ab3, y6 v ccj p14 l3 v ccp0 j1 k1 v ccp1 j16 n22 gnd p0 h1 j1 gnd p1 h16 k22 gnd a16, d13, h15, j15, n13, t16, a1, b9, b8, d4, h2, j2, n4, r8, r9, t1, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 a2, a11, a12, a21, a1, a22, aa1, aa2, aa11, aa12, aa21, aa22, ab1, ab2, ab11, ab12, ab21, ab22, b1, b2, b11, b12, b21, b22, c3, c20, d4, d19, e5, e18, f6, f17, g7, g16, h8, h15, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l1, l2, l7, l9, l10, l11, l12, l13, l14,l16, l21, l22, m1, m2, m7, m9, m10, m11, m12,m13, m14, m16, m21, m22, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14, r8, r15, t7, t16, u6, u17, v5, v18, w4, w19,y3, y20 nc 2 a11, b16 d8, d11, e6, e7, e8, e9, e12, e13, e14, e15, e16, f7, f16, g5, g6, g18, g19, h19, k4, k19, l19, m4, m19, n4, p4, p19, r4, r18, t4, t5, t17, t18, u5, u7, u16, v7, v8, v9, v10, v11, v12, v15, v16, v17, w14, y18 1. all grounds must be electrically connected at the board level. 2. nc pins should not be connected to any active signals, v cc or gnd. 3. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally.
lattice semiconductor ispgdx2 family data sheet 52 ispgdx2-64 logic signal connections signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 100 fpbga goe0 - - - - - - - h6 bk0_io0/pll_lock0 0 0n 0a 0 - - fifo0_full j6 bk0_io1 0 0p 0a 1 hsi0a_cdrrstb - fifo0_fiforstb k6 gnd 0 - - - - - - gnd bk0_io2 0 1n 0a 2 hsi0a_sinn hsi0a_recclk - g7 bk0_io3 0 1p 0a 3 hsi0a_sinp - - h7 gnd 0 - - - - - - gnd bk0_io4/pll_rst0 0 2n 0a 4 - hsi0a_rxd0/txd0 fifo0_din0/dout0 k7 bk0_io5 0 2p 0a 5 - hsi0a_rxd1/txd1 fifo0_din1/dout1 k8 bk0_io6/clk_out0 0 3n 0a 6 - hsi0a_rxd2/txd2 fifo0_din2/dout2 j8 bk0_io7 0 3p 0a 7 note 4 hsi0a_rxd3/txd3 fifo0_din3/dout3 k9 gnd 0 - - - - - - gnd tck - - - - - - - j10 resetb - - - - - - - j9 bk1_io0/pll_fbk0 0 4p 0a 8 hsi0a_sydt 5 hsi0a_rxd4/txd4 fifo0_din4/dout4 h10 bk1_io1 0 4n 0a 9 - hsi0a_rxd5/txd5 fifo0_din5/dout5 h9 bk1_io2 0 5p 0a 10 - hsi0a_rxd6/txd6 fifo0_din6/dout6 h8 bk1_io3/vref(0,1) 0 5n 0a 11 fifo0_strdb 6 hsi0a_rxd7/txd7 fifo0_din7/dout7 g10 gnd 0 - - - - - - gnd bk1_io4 0 6p 0a 12 hsi0a_soutp hsi0a_rxd8/txd8 fifo0_din8/dout8 g9 bk1_io5 0 6n 0a 13 hsi0a_soutn hsi0a_rxd9/txd9 fifo0_din9/dout9 g8 gnd 0 - - - gnd bk1_io6 0 7p 0a 14 ss_clkin1p hsi0a_sydt 5 -f9 bk1_io7 0 7n 0a 15 ss_clkin1n - fifo0_ empty f8 gclk/ce2 - - - - - - - f7 gclk/ce3 - - - - - - - e7 bk2_io0 0 8n 0b 0 ss_clkout0n - fifo1_full e8 bk2_io1 0 8p 0b 1 ss_clkout0p - fifo1_empty e9 gnd 0 - - - - - - gnd bk2_io2 0 9n 0b 2 hsi0b_soutn hsi0ba_sydt 5 -d8 bk2_io3 0 9p 0b 3 hsi0b_soutp hsi0b_rxd0/txd0 fifo1_din0 d9 gnd 0 - - - - - - gnd bk2_io4/v ref (2,3) 0 10n 0b 4 - hsi0b_rxd1/txd1 fifo1_din1/dout1 d10 bk2_io5 0 10p 0b 5 - hsi0b_rxd2/txd2 fifo1_din2/dout2 c9 bk2_io6 0 11n 0b 6 hsi0_cslock hsi0b_rxd3/txd3 fifo1_din3/dout3 c10 bk2_io7 0 11p 0b 7 note 4 hsi0b_rxd4/txd4 fifo1_din4/dout4 b10 bk3_io0 0 12p 0b 8 - hsi0b_rxd5/txd5 fifo1_din5/dout5 a9 bk3_io1 0 12n 0b 9 hsi0b_sydt 5 hsi0b_rxd6/txd6 fifo1_din6/dout6 b8 bk3_io2 0 13p 0b 10 hsi0b_rxd7/txd7 fifo1_din7/dout7 a8 bk3_io3 0 13n 0b 11 - hsi0b_rxd8/txd8 fifo1_din8/dout8 a7 gnd 0 - - - - - - gnd bk3_io4 0 14p 0b 12 hsi0b_sinp hsi0b_rxd9/txd9 fifo1_din9/dout9 c7 bk3_io5 0 14n 0b 13 hsi0b_sinn hsi0b_recclk - d7 gnd 0 - - - - - - gnd bk3_io6 0 15p 0b 14 fifo1_strdb 6 --b6 bk3_io7 0 15n 0b 15 hsi0b_cdrrstb - fifo1_fiforstb c6
lattice semiconductor ispgdx2 family data sheet 53 sel0 - - - - - - - d6 sel1 - - - - - - - d5 bk4_io0 1 16n 1a 7 0 hsi1a_cdrrstb - fifo2_fiforstb c5 bk4_io1 1 16p 1a 7 1 fifo2_strdb 6 --b5 gnd 1 - - - - - - gnd bk4_io2 1 17n 1a 7 2 hsi1a_sinn hsi1a_recclk - d4 bk4_io3 1 17p 1a 7 3 hsi1a_sinp hsi1a_rxd9/txd9 fifo2_din9/dout9 c4 gnd 1 - - - gnd bk4_io4 1 18n 1a 7 4- hsi1a_rxd8/txd8 fifo2_din8/dout8 a6 bk4_io5 1 18p 1a 7 5 cal hsi1a_rxd7/txd7 fifo2_din7/dout7 a5 bk4_io6 1 19n 1a 7 6 hsi1a_sydt 5 hsi1a_rxd6/txd6 fifo2_din6/dout6 a4 bk4_io7 1 19p 1a 7 7- hsi1a_rxd5/txd5 fifo2_din5/dout5 a3 tms - - - - - - b3 tdi - - - - - - - a2 gnd - - - - - - - gnd tdo - - - - - - - b1 toe - - - - - - - b2 bk5_io0 1 20p 1a 7 8 note 4 hsi1a_rxd4/txd4 fifo2_din4/dout4 c1 bk5_io1 1 20n 1a 7 9 hsi1_cslock hsi1a_rxd3/txd3 fifo2_din3/dout3 c2 bk5_io2 1 21p 1a 7 10 - hsi1a_rxd2/txd2 fifo2_din2/dout2 c3 bk5_io3/vref(4,5) 1 21n 1a 7 11 - hsi1a_rxd1/txd1 fifo2_din1/dout1 d1 gnd 1 - - - - - - gnd bk5_io4 1 22p 1a 7 12 hsi1a_soutp hsi1a_rxd0/txd0 fifo2_din0/dout0 d3 bk5_io5 1 22n 1a 7 13 hsi1a_soutn hsi1a_sydt 5 -d2 gnd 1 - - - - - gnd bk5_io6 1 23p 1a 7 14 ss_clkin1p - fifo2_empty e2 bk5_io7 1 23n 1a 7 15 ss_clkin1n - fifo2_full e3 gclk/ce0 - - - - - - - e4 gclk/ce1 - - - - - - - f4 bk6_io0 1 24n 1b 0 ss_clkout1n - fifo3_empty f3 bk6_io1 1 24p 1b 1 ss_clkout1p hsi1b_sydt 5 -f2 gnd 1 - - - - - - gnd bk6_io2 1 25n 1b 2 hsi1b_soutn hsi1b_rxd9/txd9 fifo3_din9/dout9 g3 bk6_io3 1 25p 1b 3 hsi1b_soutp hsi1b_rxd8/txd8 fifo3_din8/dout8 g2 gnd 1 - - - - - - gnd bk6_io4/vref(bank6,7) 1 26n 1b 4 fifo3_strdb 6 hsi1b_rxd7/txd7 fifo3_din7/dout7 g1 bk6_io5 1 26p 1b 5 - hsi1b_rxd6/txd6 fifo3_din6/dout6 h1 bk6_io6 1 27n 1b 6 - hsi1b_rxd5/txd5 fifo3_din5/dout5 h2 bk6_io7/pll_fbk1 1 27p 1b 7 hsi1b_sydt 5 hsi1b_rxd4/txd4 fifo3_din4/dout4 j1 bk7_io0 1 28p 1b 8 note 4 hsi1b_rxd3/txd3 fifo3_din3/dout3 j3 bk7_io1/clk_out1 1 28n 1b 9 - hsi1b_rxd2/txd2 fifo3_din2/dout2 k2 bk7_io2 1 29p 1b 10 - hsi1b_rxd1/txd1 fifo3_din1/dout1 j4 bk7_io3/pll_rst1 1 29n 1b 11 - hsi1b_rxd0/txd0 fifo3_din0/dout0 k3 gnd 1 - - - - - - gnd bk7_io4 1 30p 1b 12 hsi1b_sinp - - g4 bk7_io5 1 30n 1b 13 hsi1b_sinn hsi1b_recclk - h4 ispgdx2-64 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 100 fpbga
lattice semiconductor ispgdx2 family data sheet 54 gnd 1 - - - - - - gnd bk7_io6 1 31p 1b 14 hsi1b_cdrrstb - fifo3_fiforstb k5 bk7_io7/pll_lock1 1 31n 1b 15 - - fifo3_full j5 goe1 1 - - - - - - h5 1. the signals in this column route to/from the assigned pins of the associated i/o cell. 2. the signals in this column use the i/o cell. if a receiver signal is present in the i/o cell, the associated pin is available f or output only. when transmit data (txd) is present in the cell, the associated pin is available for input only. 3. the dout outputs are routed to grp through the input register of the cell and the din inputs are routed direct from the assoc iated pins in fifo only mode. in serdes with fifo mode, the full and empty ags are routed to the associated pins through the output mux and the pins. 4. if the source synchronous receiver is used in the hsi block, this pin is unavailable for another use and must be left unconne cted. 5. the sydt signal has two routing options. if direct output through the dedicated pin is used, the i/o cell (the whole hsi bloc k) is not avail- able for transmitter. the sydt in the i/o cell column is routed to the grp through the input register of the cell and frees the i/o cell for transmitter. 6. fifo_strdb ag output is used in serdes with fifo mode only. 7. syshsi source synchronous receive mode is not available for channel 1a. ispgdx2-64 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 100 fpbga
lattice semiconductor ispgdx2 family data sheet 55 ispgdx2-128 logic signal connections signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 208 fpbga toe - - - - - - p8 bk0_io0 0 0n 0a 0 - - fifo0a_full p9 bk0_io1 0 0p 0a 1 - - - t10 bk0_io2 / pll_lock2 / pll_rst2 01n0a2 -- - r10 bk0_io3 0 1p 0a 3 - hsi0a_sydt 5 fifo0a_ empty t11 gnd 0 - - - - - gnd bk0_io4 0 2n 0a 4 hsi0a_sinn hsi0a_rxd0/txd0 fifo0a_din0/dout0 p10 bk0_io5 0 2p 0a 5 hsi0a_sinp hsi0a_rxd1/txd1 fifo0a_din1/dout1 n10 bk0_io6 0 3n 6 - hsi0a_rxd2/txd2 fifo0a_din2/dout2 r11 bk0_io7 0 3p 0a 7 - hsi0a_rxd3/txd3 fifo0a_din3/dout3 t13 bk0_io8 0 4n 0a 8 note 4 hsi0a_rxd4/txd4 fifo0a_din4/dout4 p11 bk0_io9 / pll_fb2 0 4p 0a 9 - hsi0a_rxd5/txd5 fifo0a_din5/dout5 r12 bk0_io10 0 5n 0a 10 hsi0a_soutn hsi0a_rxd6/txd6 fifo0a_din6/dout6 p12 bk0_io11 0 5p 0a 11 hsi0a_soutp hsi0a_rxd7/txd7 fifo0a_din7/dout7 n12 gnd 0 - - - - - gnd bk0_io12 0 6n 0a 12 - hsi0a_rxd8/txd8 fifo0a_din8/dout8 t14 bk0_io13 0 6p 0a 13 hsi0a_sydt 5 hsi0a_rxd9/txd9 fifo0a_din9/dout9 r13 bk0_io14 0 7n 0a 14 hsi0a_cdrrstb hsi0a_recclk fifo0a_fiforstb t15 bk0_io15 / vref0 0 7p 0a 15 fifo0a_strdb 6 -- p13 goe3 - - - - - - t9 tdo - - - - - - r16 gnd 1 - - - - - gnd bk1_io0 / vref1 1 8p 0b 0 - hsi0b_sydt 5 fifo0b_full n14 bk1_io1 1 8n 0b 1 - hsi0b_rxd0/txd0 fifo0b_din0/dout0 p15 bk1_io2 1 9p 0b 2 note 4 hsi0b_rxd1/txd1 fifo0b_din1/dout1 n15 bk1_io3 1 9n 0b 3 - hsi0b_rxd2/txd2 fifo0b_din2/dout2 l14 bk1_io4 1 10p 0b 4 hsi0b_soutp hsi0b_rxd3/txd3 fifo0b_din3/dout3 m14 bk1_io5 1 10n 0b 5 hsi0b_soutn hsi0b_rxd4/txd4 fifo0b_din4/dout4 m13 bk1_io6 1 11p 0b 6 hsi0_cslock hsi0b_rxd5/txd5 fifo0b_din5/dout5 m15 bk1_io7 1 11n 0b 7 hsi0b_sydt 5 hsi0b_rxd6/txd6 fifo0b_din6/dout6 l15 bk1_io8 1 12p 0b 8 - hsi0b_rxd7/txd7 fifo0b_din7/dout7 p16 bk1_io9 1 12n 0b 9 - hsi0b_rxd8/txd8 fifo0b_din8/dout8 n16 bk1_io10 1 13p 0b 10 hsi0b_sinp hsi0b_rxd9/txd9 fifo0b_din9/dout9 k14 bk1_io11 1 13n 0b 11 hsi0b_sinn hsi0b_recclk - k13 gnd 1 - - - - - gnd bk1_io12 1 14p 0b 12 fifo0b_strdb 6 - - k15 bk1_io13 1 14n 0b 13 hsi0b_cdrrstb - fifo0b_fiforstb l16 bk1_io14 1 15p 0b 14 ss_clkin1p - - j14 bk1_io15 / clk_out2 1 15n 0b 15 ss_clkin1n - fifo0b_ empty j13 gclk/ce2 - - - - - - n8 sel2 - - - - - - k16 sel3 - - - - - - g16 gclk/ce3 - - - - - - n9 bk2_io0 2 16n 1a 7 0 ss_clkout1n - fifo1a_full h13 bk2_io1 2 16p 1a 7 1 ss_clkout1p - - h14 bk2_io2 2 17n 1a 7 2- hsi1a_sydt 5 - g15
lattice semiconductor ispgdx2 family data sheet 56 bk2_io3 2 17p 1a 7 3- hsi1a_rxd0/txd0 fifo1a_din0/dout0 f16 gnd 2 - - - - - gnd bk2_io4 2 18n 1a 7 4 hsi1a_sinn hsi1a_rxd1/txd1 fifo1a_din1/dout1 g13 bk2_io5 2 18p 1a 7 5 hsi1a_sinp hsi1a_rxd2/txd2 fifo1a_din2/dout2 g14 bk2_io6 2 19n 1a 7 6 hsi1_cslock hsi1a_rxd3/txd3 fifo1a_din3/dout3 f14 bk2_io7 2 19p 1a 7 7 note 4 hsi1a_rxd4/txd4 fifo1a_din4/dout4 f15 bk2_io8 2 20n 1a 7 8 cal hsi1a_rxd5/txd5 fifo1a_din5/dout5 d16 bk2_io9 2 20p 1a 7 9- hsi1a_rxd6/txd6 fifo1a_din6/dout6 e15 bk2_io10 2 21n 1a 7 10 hsi1a_soutn hsi1a_rxd7/txd7 fifo1a_din7/dout7 e13 bk2_io11 2 21p 1a 7 11 hsi1a_soutp hsi1a_rxd8/txd8 fifo1a_din8/dout8 e14 gnd 2 - - - - - gnd bk2_io12 2 22n 1a 7 12 hsi1a_sydt 5 hsi1a_rxd9/txd9 fifo1a_din9/dout9 c16 bk2_io13 2 22p 1a 7 13 hsi1a_cdrrstb hsi1a_recclk fifo1a_fiforstb d15 bk2_io14 2 23n 1a 7 14 fifo1a_strdb 6 -- c15 bk2_io15 / vref2 2 23p 1a 7 15 - - fifo1a_empty d14 tck - - - - - - r14 goe2 - - - - - - a9 bk3_io0 / vref3 3 24p 1b 0 - hsi1b_rxd0/txd0 fifo1b_din0/dout0 c13 bk3_io1 3 24n 1b 1 note 4 hsi1b_rxd1/txd1 fifo1b_din1/dout1 b14 bk3_io2 3 25p 1b 2 - hsi1b_rxd2/txd2 fifo1b_din2/dout2 a15 bk3_io3 3 25n 1b 3 - hsi1b_rxd3/txd3 fifo1b_din3/dout3 b13 gnd 3 - - - - gnd bk3_io4 3 26p 1b 4 hsi1b_soutp hsi1b_rxd4/txd4 fifo1b_din4/dout4 d12 bk3_io5 3 26n 1b 5 hsi1b_soutn hsi1b_rxd5/txd5 fifo1b_din5/dout5 c12 bk3_io6 3 27p 1b 6 - hsi1b_rxd6/txd6 fifo1b_din6/dout6 a14 bk3_io7 3 27n 1b 7 - hsi1b_rxd7/txd7 fifo1b_din7/dout7 / fifo1b_strdb a13 bk3_io8 3 28p 1b 8 - hsi1b_rxd8/txd8 fifo1b_din8/dout8 b12 bk3_io9 3 28n 1b 9 hsi1b_sydt 5 hsi1b_rxd9/txd9 fifo1b_din9/dout9 c11 bk3_io10 3 29p 1b 10 hsi1b_sinp hsi1b_recclk - d10 bk3_io11 3 29n 1b 11 hsi1b_sinn - - c10 gnd 3 - - - - - gnd bk3_io12 3 30p 1b 12 - hsi1b_sydt 5 fifo1b_full b11 bk3_io13 3 30n 1b 13 hsi1b_cdrrstb - fifo1b_fiforstb b10 bk3_io14 3 31p 1b 14 - - - a10 bk3_io15 3 31n 1b 15 - - fifo1b_ empty c9 reset - - - - - - a7 bk4_io0 4 32n 2a 0 - - fifo2a_empty c8 bk4_io1 / pll_lock0 / pll_rst0 4 32p 2a 1 - - - b7 bk4_io2 4 33n 2a 2 hsi2a_cdrrstb - fifo2a_fiforstb a6 bk4_io3 4 33p 2a 3 - hsi2a_sydt 5 fifo2a_full b6 gnd 4 - - - gnd bk4_io4 4 34n 2a 4 hsi2a_sinn - - c7 bk4_io5 4 34p 2a 5 hsi2a_sinp hsi2a_recclk - d7 bk4_io6 4 35n 2a 6 hsi2a_sydt 5 hsi2a_rxd9/txd9 fifo2a_din9/dout9 c6 bk4_io7 4 35p 2a 7 - hsi2a_rxd8/txd8 fifo2a_din8/dout8 b5 ispgdx2-128 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 208 fpbga
lattice semiconductor ispgdx2 family data sheet 57 bk4_io8 4 36n 2a 8 fifo2a_strdb 6 hsi2a_rxd7/txd7 fifo2a_din7/dout7 a4 bk4_io9 / pll_fb0 4 36p 2a 9 - hsi2a_rxd6/txd6 fifo2a_din6/dout6 a3 bk4_io10 4 37n 2a 10 hsi2a_soutn hsi2a_rxd5/txd5 fifo2a_din5/dout5 c5 bk4_io11 4 37p 2a 11 hsi2a_soutp hsi2a_rxd4/txd4 fifo2a_din4/dout4 d5 gnd 4 - - - - gnd bk4_io12 4 38n 2a 12 - hsi2a_rxd3/txd3 fifo2a_din3/dout3 b4 bk4_io13 4 38p 2a 13 - hsi2a_rxd2/txd2 fifo2a_din2/dout2 a2 bk4_io14 4 39n 2a 14 note 4 hsi2a_rxd1/txd1 fifo2a_din1/dout1 b3 bk4_io15 / vref4 4 39p 2a 15 - hsi2a_rxd0/txd0 fifo2a_din0/dout0 c4 goe1 - - - - - a8 tms - - - - - - r1 gnd 5 - - - - - gnd bk5_io0 / vref5 5 40p 2b 0 - - fifo2b_empty d3 bk5_io1 5 40n 2b 1 fifo2b_strdb 6 --c2 bk5_io2 5 41p 2b 2 hsi2b_cdrrstb hsi2b_recclk fifo2b_fiforstb d2 bk5_io3 5 41n 2b 3 hsi2b_sydt 5 hsi2b_rxd9/txd9 fifo2b_din9/dout9 b1 bk5_io4 5 42p 2b 4 hsi2b_soutp hsi2b_rxd8/txd8 fifo2b_din8/dout8 e3 bk5_io5 5 42n 2b 5 hsi2b_soutn hsi2b_rxd7/txd7 fifo2b_din7/dout7 e4 bk5_io6 5 43p 2b 6 - hsi2b_rxd6/txd6 fifo2b_din6/dout6 f3 bk5_io7 5 43n 2b 7 - hsi2b_rxd5/txd5 fifo2b_din5/dout5 e2 bk5_io8 5 44p 2b 8 note 4 hsi2b_rxd4/txd4 fifo2b_din4/dout4 f2 bk5_io9 5 44n 2b 9 hsi2_cslock hsi2b_rxd3/txd3 fifo2b_din3/dout3 c1 bk5_io10 5 45p 2b 10 hsi2b_sinp hsi2b_rxd2/txd2 fifo2b_din2/dout2 g3 bk5_io11 5 45n 2b 11 hsi2b_sinn hsi2b_rxd1/txd1 fifo2b_din1/dout1 g4 gnd 5 - - - - - gnd bk5_io12 5 46p 2b 12 - hsi2b_rxd0/txd0 fifo2b_din0/dout0 d1 bk5_io13 5 46n 2b 13 - hsi2b_sydt 5 -g2 bk5_io14 5 47p 2b 14 ss_clkin0p - - h4 bk5_io15 / clk_out0 5 47n 2b 15 ss_clkin0n - fifo2b_full h3 gclk/ce0 - - - - - - d9 sel0 - - - - - - f1 sel1 - - - - - - g1 gclk/ce1 - - - - - - d8 bk6_io0 6 48n 3a 0 ss_clkout0n - fifo3a_empty j4 bk6_io1 6 48p 3a 1 ss_clkout0p - - j3 bk6_io2 6 49n 3a 2 hsi3a_cdrrstb - fifo3a_fiforstb k1 bk6_io3 6 49p 3a 3 fifo3a_strdb 6 --k2 gnd 6 - - - - - gnd bk6_io4 6 50n 3a 4 hsi3a_sinn hsi3a_recclk - k4 bk6_io5 6 50p 3a 5 hsi3a_sinp hsi3a_rxd9/txd9 fifo3a_din9/dout9 k3 bk6_io6 6 51n 3a 6 - hsi3a_rxd8/txd8 fifo3a_din8/dout8 l1 bk6_io7 6 51p 3a 7 - hsi3a_rxd7/txd7 fifo3a_din7/dout7 l2 bk6_io8 6 52n 3a 8 hsi3a_sydt 5 hsi3a_rxd6/txd6 fifo3a_din6/dout6 n1 bk6_io9 6 52p 3a 9 hsi3_cslock hsi3a_rxd5/txd5 fifo3a_din5/dout5 m2 bk6_io10 6 53n 3a 10 hsi3a_soutn hsi3a_rxd4/txd4 fifo3a_din4/dout4 m4 bk6_io11 6 53p 3a 11 hsi3a_soutp hsi3a_rxd3/txd3 fifo3a_din3/dout3 m3 ispgdx2-128 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 208 fpbga
lattice semiconductor ispgdx2 family data sheet 58 gnd 6 - - - - - gnd bk6_io12 6 54n 3a 12 - hsi3a_rxd2/txd2 fifo3a_din2/dout2 l3 bk6_io13 6 54p 3a 13 note 4 hsi3a_rxd1/txd1 fifo3a_din1/dout1 n2 bk6_io14 6 55n 3a 14 - hsi3a_rxd0/txd0 fifo3a_din0/dout0 p1 bk6_io15 / vref6 6 55p 3a 15 - hsi3a_sydt 5 fifo3a_ full p2 tdi - - - - - - n3 goe0 - - - - - - t8 gnd 7 - - - - - gnd bk7_io0 / vref7 7 56p 3b 0 fifo3b_strdb 6 --t2 bk7_io1 7 56n 3b 1 hsi3b_cdrrstb hsi3b_recclk fifo3b_fiforstb r3 bk7_io2 7 57p 3b 2 hsi3b_sydt 5 hsi3b_rxd9/txd9 fifo3b_din9/dout9 p4 bk7_io3 7 57n 3b 3 - hsi3b_rxd8/txd8 fifo3b_din8/dout8 t3 bk7_io4 7 58p 3b 4 hsi3b_soutp hsi3b_rxd7/txd7 fifo3b_din7/dout7 n5 bk7_io5 7 58n 3b 5 hsi3b_soutn hsi3b_rxd6/txd6 fifo3b_din6/dout6 p5 bk7_io6 7 59p 3b 6 - hsi3b_rxd5/txd5 fifo3b_din5/dout5 r4 bk7_io7 7 59n 3b 7 note 4 hsi3b_rxd4/txd4 fifo3b_din4/dout4 t4 bk7_io8 7 60p 3b 8 - hsi3b_rxd3/txd3 fifo3b_din3/dout3 r5 bk7_io9 7 60n 3b 9 - hsi3b_rxd2/txd2 fifo3b_din2/dout2 p6 bk7_io10 7 61p 3b 10 hsi3b_sinp hsi3b_rxd1/txd1 fifo3b_din1/dout1 n7 bk7_io11 7 61n 3b 11 hsi3b_sinn hsi3b_rxd0/txd0 fifo3b_din0/dout0 p7 gnd 7 - - - - - gnd bk7_io12 7 62p 3b 12 - hsi3b_sydt 5 fifo3b_ empty r6 bk7_io13 7 62n 3b 13 - - - t6 bk7_io14 7 63p 3b 14 - - - r7 bk7_io15 7 63n 3b 15 - - fifo3b_full t7 1. the signals in this column route to/from the assigned pins of the associated i/o cell. 2. the signals in this column use the i/o cell. if a receiver signal is present in the i/o cell, the associated pin is available for output only. when transmit data (txd) is present in the cell, the associated pin is available for input only. 3. the dout outputs are routed to grp through the input register of the cell and the din inputs are routed direct from the assoc iated pins in fifo only mode. in serdes with fifo mode, the full and empty ags are routed to the associated pins through the output mux and the pins. 4. if the source synchronous receiver is used in the hsi block, this pin is unavailable for another use and must be left unconne cted. 5. the sydt signal has two routing options. if direct output through the dedicated pin is used, the i/o cell (the whole hsi bloc k) is not avail- able for transmitter. the sydt in the i/o cell column is routed to the grp through the input register of the cell and frees the i/o cell for transmitter. 6. fifo_strdb ag output is used in serdes with fifo mode only. 7. syshsi source synchronous receive mode is not available for channel 1a. ispgdx2-128 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 208 fpbga
lattice semiconductor ispgdx2 family data sheet 59 ispgdx2-256 logic signal connections signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga bk0_io0 0 0n 0a 0 - - fifo0a_full ab13 bk0_io1 0 0p 0a 1 - - - aa13 bk0_io2/ pll_lock2 01n0a2 -- - v13 bk0_io3 0 1p 0a 3 - - fifo0a_ empty v14 gnd 0 - - - - hsi0a_sydt 5 - gnd bk0_io4 0 2n 0a 4 hsi0a_sinn hsi0a_rxd0/txd0 fifo0a_din0/dout0 u12 bk0_io5 0 2p 0a 5 hsi0a_sinp hsi0a_rxd1/txd1 fifo0a_din1/dout1 u13 bk0_io6 0 3n 6 - hsi0a_rxd2/txd2 fifo0a_din2/dout2 w12 bk0_io7 0 3p 0a 7 - hsi0a_rxd3/txd3 fifo0a_din3/dout3 y13 bk0_io8 0 4n 0a 8 note 4 hsi0a_rxd4/txd4 fifo0a_din4/dout4 w13 bk0_io9/ pll_fb2 04 p0 a9 - hsi0a_rxd5/txd5 fifo0a_din5/dout5 y14 bk0_io10 0 5n 0a 10 hsi0a_soutn hsi0a_rxd6/txd6 fifo0a_din6/dout6 t12 bk0_io11 0 5p 0a 11 hsi0a_soutp hsi0a_rxd7/txd7 fifo0a_din7/dout7 t13 gnd 0 - - - - - - gnd bk0_io12 0 6n 0a 12 - hsi0a_rxd8/txd8 fifo0a_din8/dout8 ab14 bk0_io13 0 6p 0a 13 hsi0a_sydt 5 hsi0a_rxd9/txd9 fifo0a_din9/dout9 ab15 bk0_io14 0 7n 0a 14 hsi0a_cdrrstb hsi0a_recclk fifo0a_fiforstb y15 bk0_io15 0 7p 0a 15 fifo0a_strdb 6 -- w15 bk0_io16 0 8n 1a 0 - - fifo1a_full aa15 bk0_io17/ pll_rst2 08 p1 a1 -- - aa16 bk0_io18 0 9n 1a 2 - hsi1a_sydt 5 - y16 bk0_io19 0 9p 1a 3 - hsi1a_rxd0/txd0 fifo1a_din0/dout0 w16 gnd 0 - - - - - - gnd bk0_io20 0 10n 1a 4 hsi1a_soutn hsi1a_rxd1/txd1 fifo1a_din1/dout1 u14 bk0_io21/ vref0 0 10p 1a 5 hsi1a_soutp hsi1a_rxd2/txd2 fifo1a_din2/dout2 u15 bk0_io22 0 11n 1a 6 - hsi1a_rxd3/txd3 fifo1a_din3/dout3 ab16 bk0_io23 0 11p 1a 7 note 4 hsi1a_rxd4/txd4 fifo1a_din4/dout4 ab17 bk0_io24 0 12n 1a 8 - hsi1a_rxd5/txd5 fifo1a_din5/dout5 aa17 bk0_io25 0 12p 1a 9 - hsi1a_rxd6/txd6 fifo1a_din6/dout6 w17 bk0_io26 0 13n 1a 10 hsi1a_sinn hsi1a_rxd7/txd7 fifo1a_din7/dout7 t14 bk0_io27 0 13p 1a 11 hsi1a_sinp hsi1a_rxd8/txd8 fifo1a_din8/dout8 t15 bk0_io28 0 14n 1a 12 hsi1a_sydt 5 hsi1a_rxd9/txd9 fifo1a_din9/dout9 aa18 bk0_io29 0 14p 1a 13 hsi1a_cdrrstb 5 hsi1a_recclk fifo1a_fiforstb ab18 bk0_io30 0 15n 1a 14 fifo1a_strdb 6 -- w18 bk0_io31 0 15p 1a 15 - - fifo1a_empty y19 gnd 0 - - - - - - gnd goe3 - - - - - - - aa19 tdo - - - - - - - ab19 gnd 1 - - - - - - gnd bk1_io0 1 16p 0b 0 - - fifo0b_ full w21 bk1_io1 1 16n 0b 1 - hsi0b_sydt 5 - w20 bk1_io2 1 17p 0b 2 - hsi0b_rxd0/txd0 fifo0b_din0/dout0 v22 bk1_io3 1 17n 0b 3 note 4 hsi0b_rxd1/txd1 fifo0b_din1/dout1 w22 bk1_io4 1 18p 0b 4 hsi0b_sinp hsi0b_rxd2/txd2 fifo0b_din2/dout2 p16
lattice semiconductor ispgdx2 family data sheet 60 bk1_io5 1 18n 0b 5 hsi0b_sinn hsi0b_rxd3/txd3 fifo0b_din3/dout3 p17 bk1_io6 1 19p 0b 6 hsi0_cslock hsi0b_rxd4/txd4 fifo0b_din4/dout4 u18 bk1_io7 1 19n 0b 7 - hsi0b_rxd5/txd5 fifo0b_din5/dout5 v19 bk1_io8 1 20p 0b 8 - hsi0b_rxd6/txd6 fifo0b_din6/dout6 v20 bk1_io9 1 20n 0b 9 hsi0b_sydt 5 hsi0b_rxd7/txd7 fifo0b_din7/dout7 v21 bk1_io10/ vref1 1 21p 0b 10 hsi0b_soutp hsi0b_rxd8/txd8 fifo0b_din8/dout8 r16 bk1_io11 1 21n 0b 11 hsi0b_soutn hsi0b_rxd9/txd9 fifo0b_din9/dout9 r17 gnd 1 - - - - - - gnd bk1_io12 1 22p 0b 12 hsi0b_cdrrstb hsi0b_recclk fifo0b_fiforstb u19 bk1_io13 1 22n 0b 13 fifo0b_strdb 6 -- t19 bk1_io14 1 23p 0b 14 - - - u21 bk1_io15 1 23n 0b 15 - - fifo0b_empty u22 bk1_io16 1 24p 1b 0 - hsi1b_sydt 5 fifo1b_full r19 bk1_io17 1 24n 1b 1 - hsi1b_rxd0/txd0 fifo1b_din0/dout0 t20 bk1_io18 1 25p 1b 2 note 4 hsi1b_rxd1/txd1 fifo1b_din1/dout1 t21 bk1_io19 1 25n 1b 3 - hsi1b_rxd2/txd2 fifo1b_din2/dout2 t22 gnd 1 - - - - - - gnd bk1_io20 1 26p 1b 4 hsi1b_soutp hsi1b_rxd3/txd3 fifo1b_din3/dout3 n16 bk1_io21 1 26n 1b 5 hsi1b_soutn hsi1b_rxd4/txd4 fifo1b_din4/dout4 n17 bk1_io22 1 27p 1b 6 hsi1_cslock hsi1b_rxd5/txd5 fifo1b_din5/dout5 r20 bk1_io23 1 27n 1b 7 hsi1b_sydt 5 hsi1b_rxd6/txd6 fifo1b_din6/dout6 r21 bk1_io24 1 28p 1b 8 - hsi1b_rxd7/txd7 fifo1b_din7/dout7 n19 bk1_io25 1 28n 1b 9 - hsi1b_rxd8/txd8 fifo1b_din8/dout8 p20 bk1_io26 1 29p 1b 10 hsi1b_sinp hsi1b_rxd9/txd9 fifo1b_din9/dout9 p18 bk1_io27 1 29n 1b 11 hsi1b_sinn hsi1b_recclk - n18 gnd 1 - - - - - gnd bk1_io28 1 30p 1b 12 fifo1b_strdb 6 -- r22 bk1_io29 1 30n 1b 13 hsi1b_cdrrstb - fifo1b_fiforstb p22 bk1_io30 1 31p 1b 14 ss_clkin1p - - m18 bk1_io31/ clk_out2 1 31n 1b 15 ss_clkin1n - fifo1b_empty m17 gclk/ce2 - clk2p - - - - - n20 sel2 - - - - - - - n21 sel3 - - - - - - - k21 gclk/ce3 - clk2n - - - - - k20 bk2_io0/ clk_out3 2 32n 3a 7 0 ss_clkout1n - fifo3a_full k17 bk2_io1 2 32p 3a 7 1 ss_clkout1p - - k18 bk2_io2 2 33n 3a 7 2- hsi3a_sydt 5 - l17 bk2_io3 2 33p 3a 7 3- hsi3a_rxd0/txd0 fifo3a_din0/dout0 l18 gnd 2 - - - - - gnd bk2_io4 2 34n 3a 7 4 hsi3a_sinn hsi3a_rxd1/txd1 fifo3a_din1/dout1 j17 bk2_io5 2 34p 3a 7 5 hsi3a_sinp hsi3a_rxd2/txd2 fifo3a_din2/dout2 j18 bk2_io6 2 35n 3a 7 6 hsi3_cslock hsi3a_rxd3/txd3 fifo3a_din3/dout3 j22 bk2_io7 2 35p 3a 7 7 note 4 hsi3a_rxd4/txd4 fifo3a_din4/dout4 j20 bk2_io8 2 36n 3a 7 8 cal hsi3a_rxd5/txd5 fifo3a_din5/dout5 h22 bk2_io9 2 36p 3a 7 9- hsi3a_rxd6/txd6 fifo3a_din6/dout6 h21 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 61 bk2_io10 2 37n 3a 7 10 hsi3a_soutn hsi3a_rxd7/txd7 fifo3a_din7/dout7 k16 bk2_io11 2 37p 3a 7 11 hsi3a_soutp hsi3a_rxd8/txd8 fifo3a_din8/dout8 j16 gnd 2 - - - - - - gnd bk2_io12 2 38n 3a 7 12 hsi3a_sydt 5 hsi3a_rxd9/txd9 fifo3a_din9/dout9 j19 bk2_io13 2 38p 3a 7 13 hsi3a_cdrrstb hsi3a_recclk fifo3a_fiforstb h20 bk2_io14 2 39n 3a 7 14 fifo3a_strdb 6 -- g21 bk2_io15 2 39p 3a 7 15 - - fifo3a_empty g20 bk2_io16 2 40n 2a 0 - - fifo2a_full g22 bk2_io17 2 40p 2a 1 - hsi2a_sydt 5 - f22 bk2_io18 2 41n 2a 2 - hsi2a_rxd0/txd0 fifo2a_din0/dout0 f20 bk2_io19 2 41p 2a 3 note 4 hsi2a_rxd1/txd1 fifo2a_din1/dout1 f21 gnd 2 - - - - - - gnd bk2_io20/ pll_fb3 2 42n 2a 4 hsi2a_soutn hsi2a_rxd2/txd2 fifo2a_din2/dout2 h18 bk2_io21/ vref2 2 42p 2a 5 hsi2a_soutp hsi2a_rxd3/txd3 fifo2a_din3/dout3 g17 bk2_io22 2 43n 2a 6 hsi2_cslock hsi2a_rxd4/txd4 fifo2a_din4/dout4 e21 bk2_io23 2 43p 2a 7 - hsi2a_rxd5/txd5 fifo2a_din5/dout5 f19 bk2_io24 2 44n 2a 8 - hsi2a_rxd6/txd6 fifo2a_din6/dout6 e22 bk2_io25 2 44p 2a 9 hsi2a_sydt 5 hsi2a_rxd7/txd7 fifo2a_din7/dout7 d22 bk2_io26 2 45n 2a 10 hsi2a_sinn hsi2a_rxd8/txd8 fifo2a_din8/dout8 h17 bk2_io27 2 45p 2a 11 hsi2a_sinp hsi2a_rxd9/txd9 fifo2a_din9/dout9 h16 bk2_io28 2 46n 2a 12 hsi2a_cdrrstb hsi2a_recclk fifo2a_fiforstb e19 bk2_io29 2 46p 2a 13 fifo2a_strdb 6 -- f18 bk2_io30 2 47n 2a 14 - - - d20 bk2_io31 2 47p 2a 15 - - fifo2a_empty d21 gnd 2 - - - - - - gnd tck - - - - - - - b19 goe2 - - - - - - - c19 bk3_io0 3 48p 3b 0 - hsi3b_sydt 5 fifo3b_full e17 bk3_io1 3 48n 3b 1 - hsi3b_rxd0/txd0 fifo3b_din0/dout0 d18 bk3_io2 3 49p 3b 2 note 4 hsi3b_rxd1/txd1 fifo3b_din1/dout1 a19 bk3_io3 3 49n 3b 3 - hsi3b_rxd2/txd2 fifo3b_din2/dout2 a18 gnd 3 - - - - - - gnd bk3_io4 3 50p 3b 4 hsi3b_sinp hsi3b_rxd3/txd3 fifo3b_din3/dout3 g15 bk3_io5 3 50n 3b 5 hsi3b_sinn hsi3b_rxd4/txd4 fifo3b_din4/dout4 g14 bk3_io6 3 51p 3b 6 - hsi3b_rxd5/txd5 fifo3b_din5/dout5 d17 bk3_io7 3 51n 3b 7 hsi3b_sydt 5 hsi3b_rxd6/txd6 fifo3b_din6/dout6 d16 bk3_io8 3 52p 3b 8 - hsi3b_rxd7/txd7 fifo3b_din7/dout7 c18 bk3_io9 3 52n 3b 9 - hsi3b_rxd8/txd8 fifo3b_din8/dout8 b18 bk3_io10/ vref3 3 53p 3b 10 hsi3b_soutp hsi3b_rxd9/txd9 fifo3b_din9/dout9 f15 bk3_io11 3 53n 3b 11 hsi3b_soutn hsi3b_recclk - f14 gnd 3 - - - - - - gnd bk3_io12 3 54p 3b 12 fifo3b_strdb 6 -- b17 bk3_io13 3 54n 3b 13 hsi3b_cdrrstb hsi3b_recclk fifo3b_fiforstb a17 bk3_io14/ pll_rst3 3 55p 3b 14 - - - a16 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 62 bk3_io15 3 55n 3b 15 - - fifo3b_empty c16 bk3_io16 3 56p 2b 0 - hsi2b_rxd0/txd0 fifo2b_din0/dout0 d15 bk3_io17 3 56n 2b 1 note 4 hsi2b_rxd1/txd1 fifo2b_din1/dout1 d14 bk3_io18 3 57p 2b 2 - hsi2b_rxd2/txd2 fifo2b_din2/dout2 b16 bk3_io19 3 57n 2b 3 - hsi2b_rxd3/txd3 fifo2b_din3/dout3 c15 gnd 3 - - - - - - gnd bk3_io20 3 58p 2b 4 hsi2b_soutp hsi2b_rxd4/txd4 fifo2b_din4/dout4 g13 bk3_io21 3 58n 2b 5 hsi2b_soutn hsi2b_rxd5/txd5 fifo2b_din5/dout5 g12 bk3_io22 3 59p 2b 6 - hsi2b_rxd6/txd6 fifo2b_din6/dout6 b15 bk3_io23 3 59n 2b 7 fifo2b_strdb 6 hsi2b_rxd7/txd7 fifo2b_din7 /dout7 a15 bk3_io24 3 60p 2b 8 - hsi2b_rxd8/txd8 fifo2b_din8/dout8 c14 bk3_io25 3 60n 2b 9 hsi2b_sydt 5 hsi2b_rxd9/txd9 fifo2b_din9/dout9 a14 bk3_io26 3 61p 2b 10 hsi2b_sinp hsi2b_recclk - f13 bk3_io27 3 61n 2b 11 hsi2b_sinn - - f12 gnd 3 - - - - - - gnd bk3_io28 3 62p 2b 12 - hsi2b_sydt 5 fifo2b_full d13 bk3_io29 3 62n 2b 13 hsi2b_cdrrstb - fifo2b_fiforstb c13 bk3_io30/ pll_lock3 3 63p 2b 14 - - - b13 bk3_io31 3 63n 2b 15 - - fifo2b_ empty a13 resetb - - - - - - d12 bk4_io0 4 64n 4a 0 - - fifo4a_empty a10 bk4_io1/ pll_lock0 4 64p 4a 1 - - - b10 bk4_io2 4 65n 4a 2 hsi4a_cdrrstb - fifo4a_fiforstb e11 bk4_io3 4 65p 4a 3 - hsi4a_sydt 5 fifo4a_full e10 gnd 4 - - - gnd bk4_io4 4 66n 4a 4 hsi4a_sinn - - f11 bk4_io5 4 66p 4a 5 hsi4a_sinp hsi4a_recclk - f10 bk4_io6 4 67n 4a 6 hsi4a_sydt 5 hsi4a_rxd9/txd9 fifo4a_din9/dout9 c10 bk4_io7 4 67p 4a 7 - hsi4a_rxd8/txd8 fifo4a_din8/dout8 c9 bk4_io8 4 68n 4a 8 fifo4a_strdb 6 hsi4a_rxd7/txd7 fifo4a_din7 /dout7 d10 bk4_io9/ pll_fb0 4 68p 4a 9 - hsi4a_rxd6/txd6 fifo4a_din6/dout6 d9 bk4_io10 4 69n 4a 10 hsi4a_soutn hsi4a_rxd5/txd5 fifo4a_din5/dout5 g11 bk4_io11 4 69p 4a 11 hsi4a_soutp hsi4a_rxd4/txd4 fifo4a_din4/dout4 g10 gnd 4 - - - - gnd bk4_io12 4 70n 4a 12 - hsi4a_rxd3/txd3 fifo4a_din3/dout3 a9 bk4_io13 4 70p 4a 13 - hsi4a_rxd2/txd2 fifo4a_din2/dout2 c8 bk4_io14 4 71n 4a 14 note 4 hsi4a_rxd1/txd1 fifo4a_din1/dout1 b8 bk4_io15 4 71p 4a 15 - hsi4a_rxd0/txd0 fifo4a_din0/dout0 a8 bk4_io16 4 72n 5a 0 - - fifo5a_empty b7 bk4_io17/ pll_rst0 4 72p 5a 1 - - - c7 bk4_io18 4 73n 5a 2 hsi5a_cdrrstb - fifo5a_fiforstb a7 bk4_io19 4 73p 5a 3 fifo5a_strdb 6 --b6 gnd 4 - - - - - - gnd bk4_io20 4 74n 5a 4 hsi5a_soutn hsi5a_recclk - f9 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 63 bk4_io21/ vref4 4 74p 5a 5 hsi5a_soutp hsi5a_rxd9/txd9 fifo5a_din9/dout9 f8 bk4_io22 4 75n 5a 6 - hsi5a_rxd8/txd8 fifo5a_din8/dout8 d7 bk4_io23 4 75p 5a 7 - hsi5a_rxd7/txd7 fifo5a_din7/dout7 d6 bk4_io24 4 76n 5a 8 hsi5a_sydt 5 hsi5a_rxd6/txd6 fifo5a_din6/dout6 a6 bk4_io25 4 76p 5a 9 - hsi5a_rxd5/txd5 fifo5a_din5/dout5 a5 bk4_io26 4 77n 5a 10 hsi5a_sinn hsi5a_rxd4/txd4 fifo5a_din4/dout4 g9 bk4_io27 4 77p 5a 11 hsi5a_sinp hsi5a_rxd3/txd3 fifo5a_din3/dout3 g8 bk4_io28 4 78n 5a 12 - hsi5a_rxd2/txd2 fifo5a_din2/dout2 c5 bk4_io29 4 78p 5a 13 note 4 hsi5a_rxd1/txd1 fifo5a_din1/dout1 b5 bk4_io30 4 79n 5a 14 - hsi5a_rxd0/txd0 fifo5a_din0/dout0 d5 bk4_io31 4 79p 5a 15 - hsi5a_sydt 5 fifo5a_full c4 gnd 4 - - - - - gnd goe1 - - - - - b4 tms - - - - - - a4 gnd 5 - - - - - gnd bk5_io0 5 80p 4b 0 - - fifo4b_empty d2 bk5_io1 5 80n 4b 1 - - - d3 bk5_io2 5 81p 4b 2 fifo4b_strdb 6 --f5 bk5_io3 5 81n 4b 3 hsi4b_cdrrstb hsi4b_recclk fifo4b_fiforstb e4 bk5_io4 5 82p 4b 4 hsi4b_sinp hsi4b_rxd9/txd9 fifo4b_din9/dout9 j7 bk5_io5 5 82n 4b 5 hsi4b_sinn hsi4b_rxd8/txd8 fifo4b_din8/dout8 j6 bk5_io6 5 83p 4b 6 hsi4b_sydt 5 hsi4b_rxd7/txd7 fifo4b_din7/dout7 d1 bk5_io7 5 83n 4b 7 - hsi4b_rxd6/txd6 fifo4b_din6/dout6 e1 bk5_io8 5 84p 4b 8 - hsi4b_rxd5/txd5 fifo4b_din5/dout5 f4 bk5_io9 5 84n 4b 9 hsi4_cslock hsi4_rxd4/txd4 fifo4b_din4/dout4 e3 bk5_io10/ vref5 5 85p 4b 10 hsi4b_soutp hsi4b_rxd3/txd3 fifo4b_din3/dout3 h7 bk5_io11 5 85n 4b 11 hsi4b_soutn hsi4b_rxd2/txd2 fifo4b_din2/dout2 h6 gnd 5 - - - - - - gnd bk5_io12 5 86p 4b 12 note 4 hsi4b_rxd1/txd1 fifo4b_din1/dout1 e2 bk5_io13 5 86n 4b 13 - hsi4b_rxd0/txd0 fifo4b_din0/dout0 f2 bk5_io14 5 87p 4b 14 - hsi4b_sydt 5 -g4 bk5_io15 5 87n 4b 15 - - fifo4b_full h5 bk5_io16 5 88p 5b 0 - - fifo5b_empty f1 bk5_io17 5 88n 5b 1 fifo5b_strdb 6 --g1 bk5_io18 5 89p 5b 2 hsi5b_cdrrstb hsi5b_recclk fifo5b_fiforstb g3 bk5_io19 5 89n 5b 3 hsi5b_sydt 5 hsi5b_rxd9/txd9 fifo5b_din9/dout9 g2 gnd 5 - - - - - - gnd bk5_io20 5 90p 5b 4 hsi5b_soutp hsi5b_rxd8/txd8 fifo5b_din8/dout8 k7 bk5_io21 5 90n 5b 5 hsi5b_soutn hsi5b_rxd7/txd7 fifo5b_din7/dout7 k6 bk5_io22 5 91p 5b 6 - hsi5b_rxd6/txd6 fifo5b_din6/dout6 h4 bk5_io23 5 91n 5b 7 - hsi5b_rxd5/txd5 fifo5b_din5/dout5 h3 bk5_io24 5 92p 5b 8 note 4 hsi5b_rxd4/txd4 fifo5b_din4/dout4 h1 bk5_io25 5 92n 5b 9 hsi5_cslock hsi5b_rxd3/txd3 fifo5b_din3/dout3 h2 bk5_io26 5 93p 5b 10 hsi5b_sinp hsi5b_rxd2/txd2 fifo5b_din2/dout2 j5 bk5_io27 5 93n 5b 11 hsi5b_sinn hsi5b_rxd1/txd1 fifo5b_din1/dout1 k5 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 64 gnd 5 - - - - - - gnd bk5_io28 5 94p 5b 12 - hsi5b_rxd0/txd0 fifo5b_din0/dout0 j4 bk5_io29 5 94n 5b 13 - hsi5b_sydt 5 -j3 bk5_io30 5 95p 5b 14 ss_clkin0p - - l6 bk5_io31/ clk_out0 5 95n 5b 15 ss_clkin0n - fifo5b_full l5 gclk/ce0 - clk0p - - - - - l4 sel0 - - - - - - - k3 sel1 - - - - - - - k2 gclk/ce1 - clk0n - - - - - n1 bk6_io0/ clk_out1 6 96n 7a 0 ss_clkout0n - fifo7a_empty n6 bk6_io1 6 96p 7a 1 ss_clkout0p - - n5 bk6_io2 6 97n 7a 2 hsi7a_cdrrst - fifo7a_fiforstb m5 bk6_io3 6 97p 7a 3 fifo7a_strdb 6 --m6 gnd 6 - - - - - - gnd bk6_io4 6 98n 7a 4 hsi7a_sinn hsi7a_recclk - p6 bk6_io5 6 98p 7a 5 hsi7a_sinp hsi7a_rxd9/txd9 fifo7a_din9/dout9 p5 bk6_io6 6 99n 7a 6 - hsi7a_rxd8/txd8 fifo7a_din8/dout8 n3 bk6_io7 6 99p 7a 7 - hsi7a_rxd7/txd7 fifo7a_din7/dout7 n2 bk6_io8 6 100n 7a 8 hsi7a_sydt 5 hsi7a_rxd6/txd6 fifo7a_din6/dout6 p3 bk6_io9 6 100p 7a 9 hsi7_cslock hsi7a_rxd5/txd5 fifo7a_din5/dout5 p1 bk6_io10 6 101n 7a 10 hsi7a_soutn hsi7a_rxd4/txd4 fifo7a_din4/dout4 n7 bk6_io11 6 101p 7a 11 hsi7a_soutp hsi7a_rxd3/txd3 fifo7a_din3/dout3 p7 gnd 6 - - - - - - gnd bk6_io12 6 102n 7a 12 - hsi7a_rxd2/txd2 fifo7a_din2/dout2 r3 bk6_io13 6 102p 7a 13 note 4 hsi7a_rxd1/txd1 fifo7a_din1/dout1 r2 bk6_io14 6 103n 7a 14 - hsi7a_rxd0/txd0 fifo7a_din0/dout0 r1 bk6_io15 6 103p 7a 15 - hsi7a_sydt 5 fifo7a_ full t1 bk6_io16 6 104n 6a 0 - - fifo6a_empty t2 bk6_io17 6 104p 6a 1 - - - t3 bk6_io18 6 105n 6a 2 fifo6a_strdb 6 --u1 bk6_io19 6 105p 6a 3 hsi6a_cdrrstb hsi6_recclk fifo6a_fiforstb u2 gnd 6 - - - - - - gnd bk6_io20/ pll_fb1 6 106n 6a 4 hsi6a_soutn hsi6a_rxd9/txd9 fifo6a_din9/dout9 r5 bk6_io21/ vref6 6 106p 6a 5 hsi6a_soutp hsi6a_rxd8/txd8 fifo6a_din8/dout8 t6 bk6_io22 6 107n 6a 6 hsi6a_sydt 5 hsi6a_rxd7/txd7 fifo6a_din7/dout7 u4 bk6_io23 6 107p 6a 7 - hsi6a_rxd6/txd6 fifo6a_din6/dout6 v4 bk6_io24 6 108n 6a 8 - hsi6a_rxd5/txd5 fifo6a_din5/dout5 v3 bk6_io25 6 108p 6a 9 hsi6_cslock hsi6a_rxd4/txd4 fifo6a_din4/dout4 v2 bk6_io26 6 109n 6a 10 hsi6a_sinn hsi6a_rxd3/txd3 fifo6a_din3/dout3 r6 bk6_io27 6 109p 6a 11 hsi6a_sinp hsi6a_rxd2/txd2 fifo6a_din2/dout2 r7 bk6_io28 6 110n 6a 12 note 4 hsi6a_rxd1/txd1 fifo6a_din1/dout1 w1 bk6_io29 6 110p 6a 13 - hsi6a_rxd0/txd0 fifo6a_din0/dout0 v1 bk6_io30 6 111n 6a 14 - hsi6a_sydt 5 -w2 bk6_io31 6 111p 6a 15 - - fifo6a_ full w3 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 65 gnd 6 - - - - - - gnd tdi - - - - - - - aa4 goe0 - - - - - - - y4 gnd 7 - - - - - - gnd bk7_io0 7 112p 7b 0 - - fifo7b_ empty ab4 bk7_io1 7 112n 7b 1 fifo7b_strdb 6 -- ab5 bk7_io2 7 113p 7b 2 hsi7b_cdrrstb hsi7b_recclk fifo7b_fiforstb v6 bk7_io3 7 113n 7b 3 hsi7b_sydt 5 hsi7b_rxd9/txd9 fifo7b_din9/dout9 w5 bk7_io4 7 114p 7b 4 hsi7b_sinp hsi7b_rxd8/txd8 fifo7b_din8/dout8 t8 bk7_io5 7 114n 7b 5 hsi7b_sinn hsi7b_rxd7/txd7 fifo7b_din7/dout7 t9 bk7_io6 7 115p 7b 6 - hsi7b_rxd6/txd6 fifo7b_din6/dout6 w6 bk7_io7 7 115n 7b 7 - hsi7b_rxd5/txd5 fifo7b_din5/dout5 y5 bk7_io8 7 116p 7b 8 note 4 hsi7b_rxd4/txd4 fifo7b_din4/dout4 aa5 bk7_io9 7 116n 7b 9 - hsi7b_rxd3/txd3 fifo7b_din3/dout3 aa6 bk7_io10/ vref7 7 117p 7b 10 hsi7b_soutp hsi7b_rxd2/txd2 fifo7b_din2/dout2 u8 bk7_io11 7 117n 7b 11 hsi7b_soutn hsi7b_rxd1/txd1 fifo7b_din1/dout1 u9 gnd 7 - - - - - - gnd bk7_io12 7 118p 7b 12 - hsi7b_rxd0/txd0 fifo7b_din0/dout0 w7 bk7_io13 7 118n 7b 13 - hsi7b_sydt 5 -w8 bk7_io14/ pll_rst1 7 119p 7b 14 - - - ab6 bk7_io15 7 119n 7b 15 - - fifo7b_full ab7 bk7_io16 7 120p 6b 0 fifo6b_strdb 6 --y7 bk7_io17 7 120n 6b 1 hsi6b_cdrrstb hsi6b_recclk fifo6b_fiforstb aa7 bk7_io18 7 121p 6b 2 hsi6b_sydt 5 hsi6b_rxd9/txd9 fifo6b_din9/dout9 w9 bk7_io19 7 121n 6b 3 - hsi6b_rxd8/txd8 fifo6b_din8/dout8 y8 gnd 7 - - - - - - gnd bk7_io20 7 122p 6b 4 hsi6b_soutp hsi6b_rxd7/txd7 fifo6b_din7/dout7 t10 bk7_io21 7 122n 6b 5 hsi6b_soutn hsi6b_rxd6/txd6 fifo6b_din6/dout6 t11 bk7_io22 7 123p 6b 6 - hsi6b_rxd5/txd5 fifo6b_din5/dout5 aa8 bk7_io23 7 123n 6b 7 - hsi6b_rxd4/txd4 fifo6b_din4/dout4 ab8 bk7_io24 7 124p 6b 8 note 4 hsi6b_rxd3/txd3 fifo6b_din3/dout3 w10 bk7_io25 7 124n 6b 9 - hsi6b_rxd2/txd2 fifo6b_din2/dout2 y9 bk7_io26 7 125p 6b 10 hsi6b_sinp hsi6b_rxd1/txd1 fifo6b_din1/dout1 u10 bk7_io27 7 125n 6b 11 hsi6b_sinn hsi6b_rxd0/txd0 fifo6b_din0/dout0 u11 gnd 7 - - - - - - gnd bk7_io28 7 126p 6b 12 - hsi6b_sydt 5 fifo6b_ empty w11 bk7_io29/ pll_lock1 7 126n 6b 13 - - - y10 bk7_io30 7 127p 6b 14 - - - aa10 bk7_io31 7 127n 6b 15 - - fifo6b_full ab9 ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 66 to e- -- -- -- ab10 1. the signals in this column route to/from the assigned pins of the associated i/o cell. 2. the signals in this column use the i/o cell. if a receiver signal is present in the i/o cell, the associated pin is available f or output only. when transmit data (txd) is present in the cell, the associated pin is available for input only. 3. the dout outputs are routed to grp through the input register of the cell and the din inputs are routed direct from the assoc iated pins in fifo only mode. in serdes with fifo mode, the full and empty ags are routed to the associated pins through the output mux and the pins. 4. if the source synchronous receiver is used in the hsi block, this pin is unavailable for another use and must be left unconne cted. 5. the sydt signal has two routing options. if direct output through the dedicated pin is used, the i/o cell (the whole hsi bloc k) is not avail- able for transmitter. the sydt in the i/o cell column is routed to the grp through the input register of the cell and frees the i/o cell for transmitter. 6. fifo_strdb ag output is used in serdes with fifo mode only. 7. syshsi source synchronous receive mode is not available for channel 3a. ispgdx2-256 logic signal connections (continued) signal name sysio bank l vds p air/polarity gdx block mrb serdes mode i/o pin 1 serdes mode i/o cell 2 fifo mode i/o cell/pin 3 484 fpbga
lattice semiconductor ispgdx2 family data sheet 67 pa rt number description ordering information commercial f amily part number i/os voltage t pd pa ck ag e pins grade lx64v lx64v-3f100c 64 3.3 3 fpbga 100 c lx64v-5f100c 64 3.3 5 fpbga 100 c lx128v lx128v-32f208c 128 3.3 3.2 fpbga 208 c lx128v-5f208c 128 3.3 5 fpbga 208 c lx256v lx256v-35f484c 256 3.3 3.5 fpbga 484 c lx256v-5f484c 256 3.3 5 fpbga 484 c lx64b lx64b-3f100c 64 2.5 3 fpbga 100 c lx64b-5f100c 64 2.5 5 fpbga 100 c lx128b lx128b-32f208c 128 2.5 3.2 fpbga 208 c lx128b-5f208c 128 2.5 5 fpbga 208 c lx256b lx256b-35f484c 256 2.5 3.5 fpbga 484 c lx256b-5f484c 256 2.5 5 fpbga 484 c lx64c lx64c-3f100c 64 1.8 3 fpbga 100 c lx64c-5f100c 64 1.8 5 fpbga 100 c lx128c lx128c-32f208c 128 1.8 3.2 fpbga 208 c lx128c-5f208c 128 1.8 5 fpbga 208 c lx256c lx256c-35f484c 256 1.8 3.5 fpbga 484 c lx256c-5f484c 256 1.8 5 fpbga 484 c device number 64 = 64 i/os 128 = 128 i/os 256 = 256 i/os syshsi support blank = supports syshsi e = no syshsi support lx xxx x x ? xx fxxx x grade c = commercial power supply voltage v = 3.3v b = 2.5v c = 1.8v lx speed 3 = 3.0ns 32 = 3.2ns 35 = 3.5ns 5 = 5.0ns package f100 = 100-ball fpbga f208 = 208-ball fpbga f484 = 484-ball fpbga device family
lattice semiconductor ispgdx2 family data sheet 68 ?e? series commercial for further information in addition to this data sheet, the following lattice technical notes may be helpful when designing with the ispgdx2 f amily: ? sysio design and usage guidelines (tn1000) ?s ysclock pll design and usage guidelines (tn1003) ? syshsi usage guide (tn1020) ? po w er estimation in ispgdx2 devices (tn1021) f amily part number i/os voltage t pd pa ck ag e pins grade lx64ev lx64ev-3f100c 64 3.3 3 fpbga 100 c lx64ev-5f100c 64 3.3 5 fpbga 100 c lx128ev lx128ev-32f208c 128 3.3 3.2 fpbga 208 c lx128ev-5f208c 128 3.3 5 fpbga 208 c lx256ev lx256ev-35f484c 256 3.3 3.5 fpbga 484 c lx256ev-5f484c 256 3.3 5 fpbga 484 c lx64eb lx64eb-3f100c 64 2.5 3 fpbga 100 c lx64eb-5f100c 64 2.5 5 fpbga 100 c lx128eb lx128eb-32f208c 128 2.5 3.2 fpbga 208 c lx128eb-5f208c 128 2.5 5 fpbga 208 c lx256eb lx256eb-35f484c 256 2.5 3.5 fpbga 484 c lx256eb-5f484c 256 2.5 5 fpbga 484 c lx64ec lx64ec-3f100c 64 1.8 3 fpbga 100 c lx64ec-5f100c 64 1.8 5 fpbga 100 c lx128ec lx128ec-32f208ec 128 1.8 3.2 fpbga 208 c LX128EC-5F208EC 128 1.8 5 fpbga 208 c ?e? series industrial f amily part number i/os voltage t pd pa ck ag e pins grade lx64ev lx64ev-5f100i 64 3.3 5 fpbga 100 i lx64eb lx64eb-5f100i 64 2.5 5 fpbga 100 i lx64ec lx64ec-5f100i 64 1.8 5 fpbga 100 i lx128ev lx128ev-5f208i 128 3.3 5 fpbga 208 i lx128eb lx128eb-5f208i 128 3.3 5 fpbga 208 i lx128ec lx128ec-5f208i 128 3.3 5 fpbga 208 i lx256ev lx256ev-5f484i 256 3.3 5 fpbga 484 i lx256eb lx256eb-5f484i 256 2.5 5 fpbga 484 i lx256ec lx256ec-5f484i 256 1.8 5 fpbga 484 i
lattice semiconductor ispgdx2 family data sheet 69

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